Static COI Analysis for IC Diagnostic Coverage
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Solution Overview
Problem
Conventional fault simulation and diagnostic coverage (DC) calculation in integrated circuit (IC) design are inefficient, restrictive, and less accurate, particularly for complex ICs, due to large simulation lengths and restrictive fault models, leading to inadequate safety verification in critical applications like automobiles.
Innovation Solution
A computer-based EDA tool performs a static cone of influence (COI) analysis on a gate-level netlist to generate a fault-list for sequential logic, followed by register-transfer level (RTL) simulation, allowing flexible fault injection and observability assessment, thereby efficiently calculating DC of safety mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gate-level fault simulation is performed to ensure exhaustive verification, then measurement precision of diagnostic coverage is improved, but loss of time increases significantly due to large simulation length
Solution Approach 1:
The patent segments the fault simulation process into two distinct phases: (1) gate-level static COI analysis to identify dangerous faults and generate fault lists, and (2) RTL-level fault simulation to calculate diagnostic coverage. This segmentation allows each phase to operate at the appropriate abstraction level, avoiding the time cost of exhaustive gate-level simulation while maintaining accuracy for critical faults.
Solution Approach 2:
The patent transitions from gate-level simulation to RTL-level simulation, changing the dimension of abstraction. By moving to a higher level of abstraction (RTL), the simulation achieves comparable diagnostic coverage accuracy for sequential logic faults without the exponential time cost of gate-level simulation, especially for complex IC designs.
2Reliability
If conventional fault simulation is performed on gate-level netlist, then reliability of fault detection is improved, but device complexity increases due to significantly large simulation length
Solution Approach 1:
The patent performs preliminary gate-level static COI analysis to identify dangerous faults and generate targeted fault lists before proceeding to RTL simulation. This preliminary action filters out safe faults that don't require simulation, reducing the complexity of the subsequent fault simulation while maintaining reliability for detecting dangerous faults.
Solution Approach 2:
The patent changes the simulation parameters by switching from gate-level to RTL-level simulation for the actual fault propagation analysis. This parameter change reduces simulation complexity by working with higher-level abstractions while maintaining fault detection reliability through the targeted fault lists generated from static analysis.
3Reliability
If exhaustive fault simulation is performed to meet safety standards, then reliability of safety verification is improved, but productivity decreases due to inefficient simulation process
Solution Approach 1:
The patent segments the verification process into static COI analysis (for reliability assessment) and RTL fault simulation (for efficiency), allowing each to operate optimally. This segmentation maintains safety verification reliability by ensuring dangerous faults are identified and simulated, while improving productivity by avoiding exhaustive gate-level simulation of all possible faults.
Solution Approach 2:
The patent creates a simplified model by generating fault lists from gate-level static analysis and then simulating these faults at RTL level. This copying approach preserves the essential fault information needed for safety verification while enabling faster simulation execution, thus improving productivity without sacrificing reliability.
Data Source
AI summary
Embodiments disclosed herein describe systems, methods, and products for safety verification of an IC design. A computer executing an illustrative EDA tool may perform a static cone of influence (COI) analysis of a gate-level netlist of the IC design to determine whether faults injected at combinational logic at different COIs are safe or dangerous. The computer may leverage this determination to perform a register-transfer level (RTL) simulation by generating and injecting equivalent faults to sequential logic in the IC design. The computer may further flexibly allow RTL simulations under different assumptions based upon downstream observability of the faults injected to the sequential logic. Because, RTL simulations are significantly faster than the gate-level simulations, the computer may efficiently calculate DC of one or more safety mechanism in the IC design.