Parallel Flip-Flop Timing Analysis Using Quadsection Search
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing computer-aided design tools for electronic circuits require numerous iterations to determine optimal setup and hold times for flip-flops, leading to inefficiencies in timing analysis, particularly in complex VLSI circuits.
Innovation Solution
A quadsection analysis method that divides the search window into four sections using three quadsection values and performs simulations in parallel, allowing for quicker convergence on the optimal setup and hold times by adjusting the pass and fail edges based on the results of each quadsection value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional bisection analysis is used to determine setup and hold times, then the analysis is performed sequentially with fewer simulation points per iteration, but the number of iterations required increases significantly
Solution Approach 1:
The patent divides the search window into four sections using three quadsection values instead of two bisection values, creating multiple parallel analysis paths that converge faster to the optimal setup and hold times
Solution Approach 2:
The patent dynamically adjusts the search window by selectively moving pass and fail edges based on simulation results from quadsection values, optimizing the convergence process
2Speed
If parallel simulation is implemented using quadsection values, then convergence speed increases approximately twice as fast, but the complexity of the analysis system increases
Solution Approach 1:
The analysis system is segmented into multiple independent simulation threads that process quadsection values in parallel, with each thread performing identical analysis operations on different time points
Solution Approach 2:
The same analysis methodology is applied universally across multiple quadsection values simultaneously, allowing the system to maintain a single proven algorithm while achieving parallel execution
Data Source
AI summary
A computer aided design system determines the acceptable timing for a flip-flop cell. The system generates a search window having a pass edge and a fail edge and divides the search window into four sections using three quadsection values. For each of the quadsection values, the system simulates a timing analysis of the flip-flop and determines if each of the quadsection values pass or fail the analysis. The analysis may be done in parallel. If at least one of the quadsection values passes the analysis, the system causes one of the passed quadsection values to be a new pass edge for the search window. If at least one of the quadsection values fails the analysis, the system causes one of the failed quadsection values to be a new fail edge for the search window. If the search window is less than a predetermined window width, the system assigns the new pass edge as the determined timing. If the search window is not less than the predetermined window width, the system repeats the above, starting with dividing the new search window into four sections using three quadsection values.