Complementary DTC Circuit for Low-INL Fractional-N PLL Timing
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Solution Overview
Problem
Conventional fractional-N clock multipliers introduce undesired deterministic jitter due to non-linear behavior in digital-to-time converter (DTC) circuits, characterized by integral non-linearity (INL), which causes higher jitter and spurs in the output signal.
Innovation Solution
A digital-to-time converter (DTC) circuit with two DTCs, a main DTC and a complementary DTC, where each delay stage includes a capacitively loaded driver with fixed capacitance to reduce non-linear gate capacitance effects, and a low-dropout regulator to regulate the supply, maintaining constant total current load and improving linearity resilience to process, voltage, and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a digital-to-time converter (DTC) is used to cancel deterministic jitter in the output, then jitter cancellation is achieved, but circuit imperfections cause non-linear behavior characterized by higher integral non-linearity (INL)
Solution Approach 1:
The DTC circuit is divided into multiple delay stages, each contributing a portion of the total delay. This segmentation allows the circuit to achieve fine-resolution timing control while distributing the non-linearity across stages, reducing the overall INL impact on jitter cancellation performance.
Solution Approach 2:
The patent employs capacitively loaded drivers with fixed capacitance values to linearize the delay characteristic of each stage. By carefully selecting and maintaining fixed capacitance parameters, the circuit achieves more linear delay control, reducing INL while preserving jitter cancellation capability.
2Measurement precision
If delay stages use comparators with gate capacitance, then timing control is achieved, but non-linear gate capacitance effects degrade linearity
Solution Approach 1:
Fixed capacitance elements are introduced as intermediary components between the comparators and ground. These capacitance elements act as mediators that linearize the overall delay characteristic by compensating for the non-linear gate capacitance of the comparators, thereby improving linearity while maintaining precise timing control.
3Manufacturing precision
If the total current load of the two DTCs is held constant, then linearity resilience to variations is improved, but device complexity increases
Solution Approach 1:
Two DTC circuits are combined in parallel operation, with their control signals being complementary. This merging approach allows the total current load to be held constant while achieving improved linearity resilience to PVT variations. The complementary control ensures that as one DTC draws more current, the other draws less, maintaining constant total current.
Solution Approach 2:
A low-dropout regulator with constant current load is employed to provide stable voltage supply to the DTC circuits. This feedback mechanism compensates for PVT variations, ensuring that the DTC maintains its linearity characteristics across different operating conditions without requiring complex calibration circuits.
Data Source
AI summary
An apparatus includes a first digital-to-time converter (DTC) and a second DTC. The first DTC includes a sequence of delay stages. Each of the delay stages adds a delay to an input signal based on a control signal. Each delay stage includes a comparator and a capacitor coupled to an input of the comparator and to ground. The second DTC is coupled in parallel to the first DTC. The second DTC adds a delay to the input signal based on a complement of the control signal.