Complementary I/O Cells with Equalized Wiring Lengths
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Solution Overview
Problem
In electronic systems, the reliability of output signals in I/O cells with a parallel drive configuration is compromised due to uneven wiring lengths between complementary I/O cells, leading to potential signal delays and failures in reading/writing operations, especially when the number of volatile semiconductor memories changes, making it difficult to maintain sufficient driving capability.
Innovation Solution
The solution involves a semiconductor chip design with adjacent I/O cells connected through carefully aligned electrode pads and wirings, ensuring equal wiring lengths and reduced electro-current constriction, using metal film predominantly composed of aluminum, and incorporating rewiring layers with solder bumps to stabilize output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If two complementary I/O cells are coupled in parallel to increase driving capability, then the driving current is increased, but signal delay or failure may occur due to uneven wiring lengths between the cells
Solution Approach 1:
The patent applies equipotentiality by ensuring that the wiring lengths from corresponding inverter outputs to the shared electrode pads are equalized. This is achieved through careful layout design where the first and second wirings are configured to have substantially the same length, thereby maintaining equal electrical potential conditions for complementary signals and preventing signal delay differences that would compromise reliability
2Adaptability or versatility
If the number of volatile semiconductor memories is significantly increased or decreased, then the load capacity varies, but the driving capability of existing I/O cells becomes insufficient
Solution Approach 1:
The patent applies merging by combining two complementary I/O cells into a parallel drive configuration where both cells work together to drive the same electrode pads. This consolidation effectively doubles the driving capability while maintaining adaptability to varying load conditions through the complementary nature of the paired cells
3Device complexity
If wiring and coupling are carried out without attention to coupling of output portions, then the configuration is simple, but signal delay is caused by uneven wiring length
Solution Approach 1:
The patent applies preliminary action by pre-planning and designing the wiring layout to ensure equal lengths before actual manufacturing. The wiring paths are carefully routed and configured in advance to achieve substantially equal lengths from each inverter output to the shared electrode pads, preventing signal delay issues before they can manifest in the final product
Data Source
AI summary
Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.