Memory Device With Complementary Cells for Accurate In-Memory Computing
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Solution Overview
Problem
Conventional memory devices face challenges in achieving high integration and computational accuracy for in-memory computing using non-volatile memory cells, often leading to reduced reusable information per unit area and limited on/off ratio.
Innovation Solution
A memory device with a memory cell array comprising pairs of complementary non-volatile memory cells, a detection unit, and an operation unit that performs multiplication operations on input data and weight data, separated from the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-volatile memory cells are used for in-memory computing, then integration is improved and refreshing is eliminated, but computational accuracy deteriorates due to limited on/off ratio
Solution Approach 1:
The memory cell is divided into two separate non-volatile memory cells (first and second cells) that store complementary data. This segmentation allows the system to overcome the limited on/off ratio of individual non-volatile memory cells by using paired cells to represent binary states, thereby improving computational accuracy while maintaining integration benefits
Solution Approach 2:
A detection unit is introduced as an intermediary component between the non-volatile memory cells and the computation circuitry. This detection unit detects and processes the data from the complementary memory cells, enabling accurate computational operations despite the inherent limitations of non-volatile memory on/off ratios
2Adaptability or versatility
If unit memory cells are modified to implement parallel computation, then in-memory computing capability is improved, but reusable information per unit area deteriorates
Solution Approach 1:
The non-volatile memory cells are designed to serve multiple functions: they can store data in complementary fashion for normal memory operations and simultaneously function as computational units for parallel computation. This multi-functionality enables in-memory computing without modifying the basic memory cell structure, preserving reusable information capacity
Solution Approach 2:
The complementary non-volatile memory cells inherently provide the data needed for parallel computation through their complementary storage mechanism. The system uses the existing complementary data representation to perform computational operations without requiring additional peripheral circuits or significant modifications to the memory cells themselves
3Adaptability or versatility
If detection circuit and computation circuit are integrated with memory cell array, then functionality is improved, but layout complexity deteriorates
Solution Approach 1:
The memory device is segmented into distinct functional blocks: the memory cell array for data storage, the detection unit for data detection, and the computation circuit for parallel computation operations. This segmentation allows each component to be optimized independently and simplifies the overall layout by clearly defining functional boundaries and data flow paths
Data Source
AI summary
A memory device according to one embodiment includes: a memory cell array in which a plurality of unit memories are arranged in an array, each of the unit memory including a first non-volatile memory cell and a second non-volatile memory cell, which store data in a complementary manner, a detection unit that detects the data stored in the first and second non-volatile memory cells for each unit memory; and an operation unit that sets weight data based on output of the detection unit and performs a multiplication operation on input data and the weight data.