Complementary MOS Power Amplifier for Low-Voltage mmWave Linearity
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Solution Overview
Problem
Current power amplifier circuit topologies for mmWave wireless communication applications face challenges in achieving high linearity, efficiency, and wide bandwidth while operating at low supply voltages, particularly in frequencies above 6 GHz, where existing designs often compromise on output power, efficiency, or common mode rejection.
Innovation Solution
The proposed solution involves a modified inverter amplifier circuit using complementary NMOS and PMOS transistor configurations, where NMOS and PMOS transistors are connected in parallel with inductive impedance elements and reactive components, forming a complementary transistor configuration for the first stage and a non-complementary configuration for the output stage, enhancing linearity and efficiency while allowing for higher output power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional power amplifier topologies are used for mmWave applications, then output power can be achieved, but linearity and efficiency deteriorate at frequencies above 6 GHz
Solution Approach 1:
The amplifier is divided into two distinct stages: a first stage using complementary NMOS and PMOS transistors configured for high linearity, and a second stage using a single transistor type configured for high efficiency. This segmentation allows each stage to optimize for its specific function without compromising the other, resolving the contradiction between linearity and efficiency at mmWave frequencies.
Solution Approach 2:
Different transistor configurations are applied to different stages based on local requirements: the first stage uses complementary transistors with specific biasing for optimal linearity, while the second stage uses a simplified single-type transistor configuration for maximum efficiency. This local optimization enables the system to achieve both high linearity and efficiency simultaneously at mmWave frequencies.
2Power
If high output power is achieved in existing amplifier designs, then power amplification is sufficient, but efficiency and common mode rejection worsen
Solution Approach 1:
The power amplification function is segmented across two stages: the first stage handles signal conditioning with complementary transistors for good common mode rejection, while the second stage handles power amplification with a single transistor type optimized for efficiency. This segmentation enables high output power without sacrificing efficiency or common mode rejection performance.
Solution Approach 2:
Instead of using the same transistor configuration throughout for power amplification, the design inverts the approach by using complementary transistors in the first stage for signal integrity and common mode rejection, then switching to a single transistor type in the second stage for efficient power amplification. This inversion of the conventional single-configuration approach resolves the contradiction between output power and efficiency.
3Measurement precision
If complementary NMOS and PMOS transistor configurations are used in both stages, then linearity improves, but device complexity and supply voltage requirements increase
Solution Approach 1:
The complementary transistor configuration is segmented to only the first stage where it is most beneficial for linearity and common mode rejection. The second stage uses a simpler single transistor type configuration, reducing overall device complexity and supply voltage requirements while maintaining high linearity through the first stage's complementary configuration.
4Loss of energy
If high efficiency is achieved in power amplifiers, then energy consumption is reduced, but output power and linearity deteriorate at mmWave frequencies
Solution Approach 1:
The amplifier stages are segmented by function: the first stage uses complementary transistors for signal conditioning with moderate efficiency, while the second stage uses a single transistor type optimized specifically for high efficiency power amplification. This segmentation enables the second stage to achieve high efficiency without compromising the output power and linearity established by the first stage, resolving the contradiction between efficiency and output power at mmWave frequencies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves higher output power, improved linearity, and increased efficiency compared to existing topologies, with reduced supply voltage requirements, suitable for mmWave frequencies and 5G applications, while maintaining good common mode rejection and harmonic emission profiles.
Implementation Method 1
a first inductive impedance element electrically connected to a first supply voltage... an NMOS drain terminal electrically connected to the first supply voltage through the first inductive impedance element
Implementation Method 2
one or more reactive elements electrically connected to an output node configured to provide an output signal
Data Source
AI summary
The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.