Complementary Redundancy Voting Logic for SEU-Resistant Registers
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Solution Overview
Problem
Existing SEU prevention techniques, such as triple modular redundancy (TMR), are insufficient against deliberate attacks and do not address inherent vulnerabilities to malicious actors, as they rely on identical redundant elements that can be targeted simultaneously.
Innovation Solution
Implementing complementary 2(N)-bit redundancy by storing data and its complementary value in separate registers with different voltages, using voting logic to generate an output based on multiple inputs, thereby preventing SEUs and enabling error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triple modular redundancy (TMR) is used to prevent SEU, then reliability is improved, but the circuit becomes vulnerable to deliberate attacks targeting identical redundant elements
Solution Approach 1:
The patent applies asymmetry by using complementary data storage where one register stores the original data value and another register stores the complementary (inverted) data value. This asymmetric approach ensures that identical attacks cannot simultaneously affect both registers in the same manner, as they store opposite logical states. The voting logic then compares these asymmetric values to detect and correct SEUs while resisting deliberate attacks.
2Reliability
If redundant circuit elements are segregated by a fixed distance, then SEU tolerance is improved, but the vulnerability pattern becomes predictable and exploitable
Solution Approach 1:
The patent implements dynamics by making the redundant elements adaptable rather than static. The voting logic dynamically adjusts its operation based on the detected error patterns, and the complementary storage scheme allows the system to adapt to different attack scenarios. This dynamic behavior prevents attackers from exploiting fixed spatial patterns, as the system's response and internal state relationships are not predetermined.
3Ease of manufacture
If identical redundant elements are used for SEU prevention, then manufacturing is simplified, but security against malicious actors is reduced
Solution Approach 1:
The patent applies local quality by differentiating the properties of redundant storage elements based on their functional role. Instead of using identical elements throughout, the system uses one register for original data storage and another for complementary data storage. This local differentiation maintains manufacturing simplicity while enhancing security, as the distinct local properties (original vs. complementary storage) prevent uniform exploitation across all redundant elements.
Data Source
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AI summary
The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit (104) includes a data storage element (206) to store a data value, another data storage element (202) to store a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element, (204)) to store both the data value and the complementary data value, and voting logic (124) that may enable a complementary data storage scheme with inter-circuit redundancy to prevent SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.