Complementary Register Redundancy for SEU Attack Resistance
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Solution Overview
Problem
Existing techniques for preventing single event upsets (SEUs) in integrated circuits, such as triple modular redundancy (TMR), are inadequate in defending against deliberate attacks and do not effectively address vulnerabilities to single event transients (SETs) that occur due to solar radiation, as they can be exploited by malicious actors who know the approximate distance between redundant circuit elements.
Innovation Solution
The implementation of complementary 2(N)-bit redundancy, which involves storing data values and their complementary values in replicated registers with different voltages, along with configurable voting logic to detect and correct errors, thereby preventing SEUs and enhancing security against malicious attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triple modular redundancy (TMR) is used to prevent SEUs, then reliability is improved, but the circuit becomes vulnerable to deliberate attacks because redundant elements are identical and segregated by predictable distances
Solution Approach 1:
The patent applies asymmetry by using complementary data encoding where one storage element stores the original data bit and another stores the inverted complementary bit. This asymmetric representation means that a malicious actor cannot predict which specific element to target, as attacking one element without knowing its complementary partner's state is ineffective. The asymmetric voltage levels (higher voltage for logic 0, lower voltage for logic 1) further enhance this asymmetry, making the circuit unpredictable to attackers while maintaining SEU prevention capabilities.
2Reliability
If redundant circuit elements are segregated by a technology-specific distance, then SEU tolerance is improved, but the predictable spacing creates security vulnerabilities
Solution Approach 1:
The patent implements dynamics by making the voting logic configurable and reconfigurable. The voting logic can be programmed with different criteria and can dynamically adapt to detected error patterns. This dynamic capability allows the system to change its behavior based on operational conditions, preventing attackers from exploiting static, predictable patterns while maintaining adaptability to various SEU scenarios.
3Measurement precision
If identical redundant elements are used for SEU prevention, then error detection capability is improved, but the system becomes predictable and vulnerable to targeted attacks
Solution Approach 1:
The patent applies inversion by storing complementary bits instead of identical redundant bits. Rather than copying the same data bit three times as in TMR, the system stores the original bit and its inverse in separate storage elements. This inversion approach maintains error detection capability (since discrepancies can still be detected) while eliminating predictability, as attackers cannot determine which element contains the original value and which contains the complement without additional information.
Data Source
AI summary
The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit includes a data storage element to store a data value, another data storage element to store a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element) to store both the data value and the complementary data value, and voting logic that may enable a complementary data storage scheme with inter-circuit redundancy to prevent SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.