Complementary TFT Drive Back-Plate Simplified Patterning
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Solution Overview
Problem
The manufacturing process of complementary thin film transistor drive back-plates for active matrix organic light emitting diode panels is complex and costly, requiring numerous patterning processes, which hinders the development of lighter and thinner panel technologies.
Innovation Solution
A simplified manufacturing method involving fewer masking/photolithography processes, where a lower semiconductor layer with P-type active layers is formed, followed by a gate insulating layer, lower electrode layer, upper semiconductor layer with oxide material, isolation insulating protective layer, upper electrode layer, and pixel defining layer, reducing the number of steps and thickness while maintaining functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional manufacturing process with multiple patterning processes is used, then device functionality is ensured, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent merges multiple patterning processes into a single photolithography step by designing electrode patterns that are formed simultaneously. The lower electrode layer and upper electrode layer are patterned in one exposure process, eliminating the need for sequential masking and photolithography steps, thereby simplifying the manufacturing process while maintaining device functionality
Solution Approach 2:
The single photolithography process serves multiple functions: it defines the lower electrode patterns, establishes alignment references for subsequent steps, and creates the overall device layout. This multi-functional approach replaces multiple specialized patterning steps, reducing process complexity and manufacturing cost
2Reliability
If multiple thin film layers and patterning processes are used, then transistor performance is achieved, but panel thickness increases
Solution Approach 1:
The patent employs thin film transistor structures where all active layers (lower semiconductor layer, gate insulating layer, upper semiconductor layer) are deposited as thin films rather than bulk materials. This maintains transistor performance through proper film thickness control while minimizing overall panel thickness
Solution Approach 2:
The patent implements a nested structure where the lower electrode layer is positioned within the same vertical plane as the lower semiconductor layer, and the upper electrode layer is integrated with the upper semiconductor layer. This nested arrangement eliminates the need for separate thick electrode structures, reducing overall panel thickness while maintaining electrical functionality
3Manufacturing precision
If numerous masking and photolithography processes are used, then precise device patterns are formed, but manufacturing time and cost increase
Solution Approach 1:
The patent combines multiple patterning operations into a single photolithography step, forming all electrode patterns (lower electrode and upper electrode) simultaneously. This merging approach maintains pattern precision through proper mask design while dramatically improving manufacturing efficiency by reducing the number of process cycles
Solution Approach 2:
The patent performs preliminary pattern design in the mask layer, where alignment marks and electrode patterns are pre-configured to enable single-step formation. This preliminary action ensures that subsequent processing steps can proceed with high precision without requiring multiple iterative patterning operations, thereby improving productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly reduces the number of patterning processes, lowers fabrication costs, and results in a lighter and thinner complementary thin film transistor drive back-plate, enhancing manufacturing efficiency and panel performance.
Implementation Method 1
conducting a plasma treatment on the oxide semiconductor material corresponding to the region of the pixel electrode
Data Source
AI summary
A complementary thin film transistor drive back-plate and manufacturing method thereof, a display panel. The method comprises: providing a lower semiconductor layer on a base substrate (101), and forming a P-type semiconductor active layer (103); providing a gate insulating layer (107) on the lower semiconductor layer; providing a lower electrode layer on the gate insulating layer (107), and forming a P-type transistor gate electrode (108), an N-type transistor source electrode (109) and an N-type transistor drain electrode (110); providing an upper semiconductor layer on the lower electrode layer, and forming a pixel electrode (111) and an N-type semiconductor active layer (112); providing an isolation insulating protective layer (113) on the upper semiconductor layer, and forming contact holes (114) and a protection unit (115); providing an upper electrode layer on the isolation insulating protective layer (113), and aiming a P-type transistor source electrode (116), a P-type transistor drain electrode (117) and an N-type transistor gate electrode (118); and providing a pixel defining layer (119) on the upper electrode layer, and forming a pixel connection opening (120).