Composite Capacitor Layout for Higher Capacitance in Compact Chips
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Solution Overview
Problem
The increase in chip area due to the formation of trench capacitors at the outer peripheral edge of semiconductor devices necessitates a solution that allows for the integration of multiple capacitor elements without expanding the semiconductor device's footprint.
Innovation Solution
A composite capacitor is formed to surround the element formation portion in plan view, utilizing a configuration that includes impurity diffusion layers, insulating films, and conductive laminates to integrate multiple capacitor elements without increasing the chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If trench capacitors are formed at the outer peripheral edge of the semiconductor device, then the capacitance capacity is improved, but the chip area increases
Solution Approach 1:
The patent transitions from a planar arrangement of capacitor elements to a three-dimensional stacked configuration. Multiple capacitor elements are arranged vertically in layers, with upper and lower electrode patterns alternately positioned at different heights. This vertical stacking enables increased capacitance capacity without expanding the horizontal chip footprint, effectively resolving the contradiction between capacitance capacity and chip area.
2Area of stationary object
If multiple capacitor elements are integrated monolithically, then the chip area is reduced, but the device complexity increases
Solution Approach 1:
The capacitor structure is segmented into multiple discrete capacitor elements arranged in series or parallel configurations. Each capacitor element consists of separated upper and lower electrode patterns with insulating films between them. This segmentation allows for modular integration of multiple capacitor elements within a compact area, reducing the overall chip area while managing structural complexity through systematic repetition of standardized units.
Solution Approach 2:
The patent employs a nested arrangement where multiple capacitor elements are stacked vertically within each other. Upper electrode patterns of lower capacitors are positioned beneath lower electrode patterns of upper capacitors, creating a nested three-dimensional structure. This nesting approach maximizes space utilization and integrates multiple capacitor elements into a compact volume, reducing chip area without proportionally increasing structural complexity.
Data Source
AI summary
A semiconductor device of the present disclosure includes a semiconductor substrate having an element formation portion and a composite capacitor formed to surround the element formation portion in plan view. The composite capacitor has a plurality of capacitor elements electrically connected in parallel.