Composite Semiconductor Chip Dicing Area Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing size and thickness while maintaining manufacturing efficiency, as existing methods require significant space between chips and numerous processes, leading to inefficiencies and limitations in reducing the size of the wiring substrate.
Innovation Solution
A semiconductor device design featuring a composite chip with two or more semiconductor chips connected by a dicing area, allowing for a reduced wiring substrate size and improved manufacturing efficiency by eliminating the need for gaps between chips and simplifying the resin filling process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple semiconductor chips are mounted with spaces between them on a wiring substrate, then resin filling ability is improved, but the size of the wiring substrate cannot be reduced
Solution Approach 1:
The patent merges multiple semiconductor chips into a single composite chip structure by connecting them through a dicing area. This integration eliminates the need for spaces between separate chips while maintaining manufacturability, as the composite chip is treated as one unified component during resin filling and mounting processes.
Solution Approach 2:
The patent transitions from a two-dimensional arrangement of separate chips on a substrate to a three-dimensional integrated composite chip structure. By stacking and connecting multiple chips vertically through the dicing area, the design reduces the horizontal footprint on the wiring substrate while preserving resin filling capability.
2Adaptability or versatility
If multiple semiconductor chips are mounted one by one over the wiring substrate, then mounting flexibility is improved, but the number of processes increases and manufacturing efficiency decreases
Solution Approach 1:
The patent combines multiple semiconductor chips into a single composite chip that is mounted as one unit on the wiring substrate. This merging reduces the number of mounting operations from multiple individual chip mountings to a single composite chip mounting process, thereby improving manufacturing efficiency while maintaining the flexibility to configure different chip combinations during the design phase.
Solution Approach 2:
The patent performs preliminary actions by pre-connecting and integrating multiple semiconductor chips into a composite chip structure before mounting onto the wiring substrate. The dicing area is prepared in advance to establish electrical connections between chips, so that when the composite chip is mounted, all connections are already in place, eliminating the need for subsequent individual mounting and wiring processes.
3Ease of manufacture
If spaces of 2.5 mm are provided between semiconductor chips, then resin filling is possible, but two-bump-shaped recessed warpage occurs
Solution Approach 1:
The patent eliminates the spaces between semiconductor chips by merging them into a composite chip structure. This removes the cause of two-bump-shaped recessed warpage while still allowing resin filling through the integrated dicing area, thereby achieving both warpage reduction and manufacturability.
Solution Approach 2:
The patent converts the potential harm of tight chip spacing (which could cause warpage) into a benefit by integrating chips through the dicing area. The dicing area design allows resin to flow and fill the integrated structure uniformly, transforming what would be a warpage-inducing configuration into a warpage-reducing integrated design.
Data Source
AI summary
A semiconductor device includes a composite chip mounted over a wiring substrate, the composite chip including a first area, a second area that is provided independently from the first area, and a third area including a first material between the first and second areas. The first area includes a first circuit formed in the first area, and the second area includes a second circuit formed in the second area. The first area is spaced apart from the second area by the first material.