Composite Chiplet Annular Via Structure for Warpage Control
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Solution Overview
Problem
Current IC integration techniques face limitations such as high cost, low insertion efficiency, and increased z-height due to latency and energy efficiency issues in MCP packaging, and limited interconnect density in wafer-level stacking and die stacking, which hinder the performance and yield of integrated circuit devices.
Innovation Solution
The implementation of quasi-monolithic hierarchical integration by recursively coupling chiplets with hybrid direct interconnects, including through-connections and annular structures to mitigate warpage and stress, allowing for sub 10 micrometer pitch die-to-die interconnects and improved vertical and lateral interconnect densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wafer-level stacking is used to increase interconnect density, then the number of electrical connections can be increased, but the interconnect density is limited by TSV density and cost
Solution Approach 1:
The patent divides the interconnect structure into multiple segments: TSVs for vertical connections, annular structures for stress mitigation, and hybrid interconnect regions for enhanced density. This segmentation allows each component to optimize its function without being constrained by the limitations of a monolithic TSV approach.
Solution Approach 2:
The patent employs composite interconnect structures combining different materials and geometries - copper TSVs, annular stress-mitigating structures, and hybrid interconnect regions with varying pitch densities. This composite approach enables simultaneous optimization of electrical performance, mechanical stability, and interconnect density.
2Adaptability or versatility
If die stacking is performed after thick metallization fabrication, then flexibility in die selection is improved, but interconnect density is limited by the thick metallization pitch
Solution Approach 1:
The patent performs preliminary stress mitigation and interconnect formation actions before final die stacking. Annular structures are formed in advance to prevent warpage, and hybrid interconnect regions are prepared with optimized pitch configurations before the actual die attachment, enabling both flexibility and high density.
Solution Approach 2:
The patent transitions from planar metallization to three-dimensional hybrid interconnect structures. By utilizing vertical TSVs combined with lateral hybrid interconnect regions and annular structures, the design achieves high interconnect density in multiple dimensions rather than being constrained to a single planar layer.
3Power
If through substrate vias are used to support signaling and power, then power and signal delivery is improved, but TSV density is low and cost is high
Solution Approach 1:
The patent applies different interconnect qualities to different regions: high-density TSVs in critical power and signal regions, hybrid interconnects in intermediate regions, and stress-mitigating annular structures in less critical areas. This local quality differentiation optimizes power and signal delivery where needed while reducing overall complexity and cost.
Solution Approach 2:
The patent introduces annular structures as intermediary elements between TSVs and the die substrate. These annular structures serve as stress-mitigating mediators that prevent warpage caused by TSV formation, enabling higher TSV density without the usual mechanical reliability problems that would increase cost.
4Reliability
If MCP packaging is used to combine heterogeneous IC chips, then product performance can be improved, but latency and energy efficiency are reduced
Solution Approach 1:
The patent merges multiple IC chips into a unified composite chiplet using hybrid direct interconnects. By combining heterogeneous chips at the wafer level with optimized interconnect structures, the design achieves monolithic-like performance with reduced latency compared to traditional MCP packaging, while maintaining the performance benefits of heterogeneous integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and yield of integrated circuit devices by improving interconnect density and reducing warpage, thereby addressing the limitations of existing IC integration techniques.
Implementation Method 1
annular structures to mitigate warpage and stress
Data Source
Figure 1A~1B
Figure 2
Figure 3A~3B
AI summary
Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.