Composite IC Chip Vias for Heterogeneous Integration

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Solution Overview

Problem

Monolithic silicon fabrication methods and heterogeneous integration techniques face limitations such as restricted device architecture, high fabrication costs, lower insertion efficiencies, and large z-heights, which hinder the performance of integrated circuit (IC) devices.

Innovation Solution

The integration of small embedded chips, referred to as chiplets, within the metallization levels of a host IC chip, allowing for high-density interconnection and direct bonding through metal interdiffusion, with through-chiplet vias and cantilevered vias for improved power and signal delivery, enabling efficient assembly using standard package tools.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If heterogeneous integration techniques are used to integrate independently fabricated dies, then device architecture flexibility is improved, but fabrication costs increase and insertion efficiency decreases

Engineering Contradiction:

Improvedevice architecture flexibilityVSAvoidfabrication cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent merges the host chip fabrication process with chiplet integration into a single unified process. The chiplet is integrated within metallization levels of the host chip during the same fabrication sequence, eliminating separate heterogeneous integration steps and reducing overall fabrication costs while maintaining architectural flexibility.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the integrated circuit into a host chip and separate chiplets that are integrated within metallization levels. This segmentation allows independent fabrication of chiplets followed by integration during host chip processing, providing architectural flexibility without requiring expensive post-fabrication heterogeneous integration.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If heterogeneous integration techniques are used to integrate independently fabricated dies, then device architecture flexibility is improved, but insertion efficiency decreases

Engineering Contradiction:

Improvedevice architecture flexibilityVSAvoidinsertion efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent performs preliminary actions by integrating the chiplet within metallization levels during the host chip fabrication process itself, rather than attempting integration after host chip completion. This preliminary integration approach significantly improves insertion efficiency by utilizing existing fabrication infrastructure and process steps.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If traditional heterogeneous integration is used, then device architecture flexibility is improved, but z-height increases

Engineering Contradiction:

Improvedevice architecture flexibilityVSAvoidz-height

Core Design Contradiction:

Adaptability or versatilityVSLength of stationary object

Solution Approach 1:

The patent applies the nesting principle by placing the chiplet inside the metallization levels of the host chip, effectively embedding it within the existing structure. This nested configuration minimizes the overall z-height of the integrated device while maintaining the architectural benefits of heterogeneous integration.

Inventive Principle:

Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances IC performance by reducing parasitic losses, improving power and signal delivery, and allowing for standard package assembly, thus overcoming the limitations of traditional methods.

Implementation Method 1

direct bonding through metal interdiffusion

Methodology Applied

Scientific EffectMetal interdiffusion: Diffusion Welding

Data Source

PatentUS11694986B2Vias in composite IC chip structures

Publication Date: 2023.07.04 INTEL CORP

AI summary

A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.