Tunable Composite Interposer for Thermal Stress Reduction
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Solution Overview
Problem
Conventional through-silicon vias (TSVs) in semiconductor chips reduce available space for active circuitry, increase production costs, and face reliability challenges due to stress from coefficient of thermal expansion (CTE) mismatch and non-optimal stress distribution, which complicates the interconnection of microelectronic devices in compact, high-performance applications.
Innovation Solution
A composite interposer structure comprising a substrate element with a support element, where the support element has a CTE of less than 12 ppm/°C and a compliant dielectric layer to reduce stress, allowing for closer pitch of conductive vias and terminals, and a conductor layer for direct electrical connection, enhancing thermal expansion compatibility and reducing mechanical stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional through-silicon vias (TSVs) are used to connect bond pads, then electrical connection is achieved, but the available space for active circuitry is reduced and production cost increases
Solution Approach 1:
The patent introduces an interposer structure as an intermediary component between the semiconductor chip and the substrate. This interposer contains conductive vias that provide electrical connection pathways, allowing the chip to be connected without requiring large TSV holes through the entire chip thickness. The interposer acts as a mediator that enables electrical connectivity while preserving chip area for active circuitry.
Solution Approach 2:
The patent moves the electrical connection function from the vertical dimension (through-chip TSVs) to a hybrid structure where connections are established through the interposer layer. By distributing conductive vias throughout the interposer thickness and using multiple bonding interfaces, the solution transitions from a single through-hole approach to a multi-layered connection architecture that conserves chip area.
2Reliability
If conventional TSV holes are used, then electrical connection is provided, but production cost increases
Solution Approach 1:
The interposer serves as a mediator that simplifies the manufacturing process by separating the chip fabrication from the connection formation. The interposer can be pre-fabricated with conductive vias and then bonded to the chip, allowing standard chip manufacturing processes to be used without expensive TSV drilling and filling operations on the chip itself.
Solution Approach 2:
The patent segments the electrical connection function into two separate components: the chip with bond pads and the interposer with conductive vias. This segmentation allows each component to be optimized and manufactured independently using appropriate processes, reducing the overall production cost compared to forming complete through-chip connections.
3Reliability
If conventional vias with thin dielectric insulation are used, then electrical connection is achieved, but stress reliability deteriorates due to CTE mismatch
Solution Approach 1:
The interposer is constructed as a composite structure with multiple materials having different mechanical and thermal properties. The conductive vias are surrounded by dielectric material, and the interposer substrate itself may be composed of materials selected to match the thermal expansion characteristics of the chip, reducing CTE mismatch stress.
Solution Approach 2:
The patent changes the physical parameters of the connection structure by using thicker dielectric insulation around the conductive vias in the interposer compared to conventional TSV structures. This parameter change increases the stress distribution volume and reduces stress concentration, improving reliability under thermal cycling conditions.
4Volume of moving object
If chips are packed compactly to reduce device size, then portability is improved, but thermal expansion stress increases due to CTE mismatch with substrate
Solution Approach 1:
The interposer acts as a stress-absorbing intermediary between the chip and the substrate. Its composite structure with matched CTE properties serves as a buffer that accommodates differential thermal expansion, protecting the chip from stress while enabling compact packaging arrangements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The composite interposer structure minimizes silicon usage, reduces production costs, and improves electrical interconnection reliability by reducing stress and enhancing thermal expansion compatibility, enabling more compact and efficient packaging of microelectronic devices.
Implementation Method 1
The body can have a coefficient of thermal expansion ("CTE") of less than 12 parts per million per degree Celsius ("ppm/° C."). The support element can reduce stress due to CTE mismatch between the conductive material of the via and the material of the substrate.
Implementation Method 2
Conventional vias may have reliability challenges because of a non-optimal stress distribution radiating from the vias and a mismatch of the coefficient of thermal expansion (CTE). The support element can reduce stress due to CTE mismatch.
Data Source
AI summary
A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness. The support element can have a body of at least one of dielectric or semiconductor material exposed at a second surface of the support element, openings extending through a thickness of the body, conductive vias extending within at least some of the openings in a direction of the thickness of the body, and terminals exposed at a first surface of the support element. The second surface of the support element can be united with the second surface of the substrate element. The terminals can be electrically connected with the contacts through the conductive vias and the electrically conductive structure.