Composite Mask Sidewall Spacers for Double Patterning

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Solution Overview

Problem

Current microelectronic fabrication methods using double patterning techniques face challenges in forming fine patterns with intervals less than the minimum pitch exposed by existing equipment, particularly in preventing the pitting phenomenon and achieving precise etching in semiconductor devices.

Innovation Solution

The method involves forming an etching target layer on a substrate with a sacrificial layer, creating sidewall spacers, and using these spacers and sacrificial patterns as masks to etch the target layer in different regions, allowing for the formation of precise patterns in cell, connection, and peripheral regions, while preventing pitting by controlling the etching process and using special patterning techniques.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If double patterning techniques are used to form fine patterns with intervals less than minimum pitch, then pattern precision is improved, but the pitting phenomenon occurs and manufacturing complexity increases

Engineering Contradiction:
Improvepattern precisionVSAvoidpitting phenomenon
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies segmentation by dividing the patterning process into multiple distinct stages: first forming a sacrificial pattern, then creating sidewall spacers on the sacrificial pattern, removing the sacrificial pattern, and finally etching the target layer. This multi-stage approach enables formation of fine patterns with intervals below the exposure equipment's minimum pitch while controlling the pitting phenomenon through selective etching conditions at each stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs preliminary action by forming the sacrificial pattern and sidewall spacers before the actual etching of the target layer. The sidewall spacers are formed as preliminary structures that serve as etch masks, and the sacrificial pattern is removed in advance to expose the target layer for precise etching. This preliminary preparation prevents pitting by establishing proper masking structures before the critical etching step.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If double patterning techniques are used to form fine patterns, then pattern precision is improved, but processing time and costs increase

Engineering Contradiction:
Improvepattern precisionVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent merges multiple functions into the sidewall spacer structure, which simultaneously serves as an etch mask for the target layer and defines the final pattern geometry. The sacrificial pattern and sidewall spacers work together as an integrated masking system, eliminating the need for separate photolithography steps and reducing overall processing time while maintaining high pattern precision.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If sidewall spacers are used as etch masks, then pattern precision is improved, but the complexity of the etching process increases

Engineering Contradiction:
Improveetching precisionVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The sidewall spacers are formed through self-aligned processes where the spacer material automatically deposits on the sidewalls of the sacrificial pattern, ensuring precise positioning without requiring additional alignment steps. The spacers serve as self-formed etch masks that automatically define the etching boundaries, reducing process complexity while achieving high etching precision through the self-aligned nature of the formation process.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8921233B2Microelectronic fabrication methods using composite layers for double patterning
Publication Date: 2014.12.30 SAMSUNG ELECTRONICS CO LTD
  • US8921233B2 patent drawing
  • US8921233B2 patent drawing
  • US8921233B2 patent drawing

AI summary

Some embodiments provide microelectronic fabrication methods in which a sacrificial pattern is formed on a substrate. A spacer formation layer is formed on the substrate, the spacer formation layer covering the sacrificial pattern. The spacer formation layer is etched to expose an upper surface of the sacrificial pattern and to leave at least one spacer on at least one sidewall of the sacrificial pattern. A first portion of the sacrificial pattern having a first width is removed while leaving intact a second portion of the sacrificial pattern having a second width greater than the first width to thereby form a composite mask pattern including the at least one spacer and a portion of the sacrificial layer. An underlying portion of the substrate is etched using the composite mask pattern as an etching mask.