Composite Pillar FeFET Memory Array With High-k Buffer Layer
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits has led to increased complexity in processing and manufacturing, particularly in 3D memory devices, where challenges such as low mobility of poly-silicon channels, interfacial layer breakdown, and charge trapping issues affect the reliability and endurance of ferroelectric field effect transistors (FeFETs).
Innovation Solution
A 3D memory device is proposed with a buffer layer of high dielectric constant between the ferroelectric layer and the channel layer to reduce interfacial charge trapping, enhancing switchable performance, decreasing operation voltage, and increasing the operation window, thereby improving reliability and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buffer layer of high dielectric constant is introduced between the ferroelectric layer and the channel layer, then interfacial charge trapping is reduced and reliability is improved, but device structure and manufacturing complexity increase
Solution Approach 1:
A buffer layer made of high dielectric constant material (such as hafnium oxide, hafnium zirconium oxide, or hafnium aluminum oxide) is introduced as an intermediary layer between the ferroelectric layer and the channel layer. This buffer layer acts as a mediator that reduces interfacial charge trapping while maintaining the functional relationship between the ferroelectric and channel layers, thereby improving reliability without directly modifying the core functional structures.
Solution Approach 2:
The buffer layer is constructed using composite material systems, specifically high dielectric constant materials such as hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO3), or hafnium aluminum oxide (HfAlO3). These composite material choices provide both the high dielectric constant needed for charge trapping reduction and compatibility with existing semiconductor fabrication processes.
2Use of energy by moving object
If the buffer layer is introduced to reduce interfacial charge trapping, then operation voltage decreases and operation window increases, but processing and manufacturing complexity increase
Solution Approach 1:
The buffer layer enables changes in key operational parameters: operation voltage is reduced and operation window is increased by modifying the interfacial electrical characteristics between the ferroelectric and channel layers. The high dielectric constant material in the buffer layer alters the electric field distribution, allowing for lower operating voltages while maintaining or enhancing the memory window.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of a high dielectric constant buffer layer between the ferroelectric and channel layers in 3D memory devices addresses charge trapping issues, enhancing reliability and endurance by reducing interfacial charge trapping and lowering operation voltage, thus improving the overall performance of the memory device.
Implementation Method 1
A 3D memory device is proposed with a buffer layer of high dielectric constant between the ferroelectric layer and the channel layer to reduce interfacial charge trapping
Data Source
AI summary
Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.