Composite Spacer Structures for High-Density Flash Memory
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to achieve high density and smaller feature sizes in non-volatile memory arrays while maintaining effective electrical isolation and coupling ratios, as traditional methods struggle to reduce parasitic capacitances and achieve equal line and space sizes below the minimum resolvable feature size of photolithographic processes.
Innovation Solution
The use of composite spacer structures and double spacer patterning techniques allows for the formation of dual control gate non-volatile flash memory storage elements, enabling the creation of equal line and space sizes and electrical isolation between active areas, even at dimensions below the minimum resolvable feature size, through a method involving multiple layers of spacer materials and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional photolithographic processes are used to reduce feature sizes, then storage capacity increases, but the minimum resolvable feature size limits further density improvement
Solution Approach 1:
The patent applies segmentation by dividing the pattern formation process into multiple stages using sequential spacer deposition. Instead of attempting to define all features in a single lithography step, the process segments pattern formation into: (1) initial mandrel formation, (2) first spacer deposition to define intermediate features, (3) mandrel removal, and (4) second spacer deposition to define final high-density features. This multi-stage segmentation enables feature sizes below the single-step lithographic resolution limit.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical spacer structures. By depositing spacers conformally on vertical sidewalls of mandrels and using the spacer thickness (vertical dimension) to define the horizontal feature size, the process overcomes the lateral resolution limit of photolithography. The critical dimension is controlled by vertical film thickness rather than lateral light diffraction limits.
2Quantity of substance
If feature sizes are reduced to increase density, then storage capacity improves, but electrical isolation between adjacent structures becomes difficult to maintain
Solution Approach 1:
The spacer structures serve dual functions: they define the pattern geometry while simultaneously providing electrical isolation. The dielectric spacer material inherently provides electrical insulation between adjacent conductive features, eliminating the need for separate isolation processes. The spacer's thickness and material properties self-determine both the dimensional precision and electrical isolation quality.
Solution Approach 2:
The patent employs composite material structures where spacers are formed from dielectric materials that combine pattern-defining capabilities with electrical isolation properties. The composite structure includes: conductive fill material for charge storage, dielectric spacer material for isolation and patterning, and tunnel dielectric layers for charge injection. This material composite approach enables simultaneous achievement of high density and reliable electrical isolation.
3Reliability
If dual control gate structures are formed to improve coupling ratios, then memory performance improves, but fabrication complexity increases
Solution Approach 1:
The spacer formation process serves multiple functions simultaneously: it defines the pattern geometry of control gates, provides electrical isolation between structures, and establishes the vertical alignment for dual gate formation. This multi-functionality reduces fabrication complexity by eliminating separate steps for patterning and isolation that would otherwise be required for dual control gate structures.
Solution Approach 2:
The patent performs preliminary spacer deposition and pattern definition before forming the control gate electrodes. By pre-establishing the precise geometric framework and isolation structures through spacer formation, the subsequent control gate fabrication becomes simpler and more reliable. The spacers are formed in advance to guide the alignment and positioning of the dual control gates, reducing the complexity of the overall fabrication sequence.
Data Source
AI summary
Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size are possible. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.