Compound FET With Matched Gates For Multiple Pinch-Off Voltages
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Solution Overview
Problem
The manufacturing of compound field effect transistors (FETs) with multiple pinch-off voltages is complex and costly due to the need for separate steps of masking, etching, and metal deposition to create recesses of different depths, reducing yield and increasing costs.
Innovation Solution
A compound FET design with matched gates of the same effective thickness but different lengths, sharing a common semiconductor and ohmic contact layer, and etching recesses of the same depth simplifies the manufacturing process, allowing for multiple pinch-off voltages without the need for complex depth variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate steps of masking, etching and metal deposition are used to produce recesses of different depths, then multiple pinch-off voltages are achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The invention changes the parameter from gate depth to gate length to achieve different pinch-off voltages. Instead of varying the depth of recesses (which requires multiple etching steps), the patent uses gates of the same depth but different lengths. This parameter substitution maintains the ability to achieve multiple pinch-off voltages while simplifying the manufacturing process to a single etching depth.
Solution Approach 2:
The invention transitions from varying depth (vertical dimension) to varying length (horizontal dimension) to achieve different pinch-off voltages. By moving the differentiation from the vertical dimension (recess depth) to the horizontal dimension (gate length), the patent eliminates the need for multiple masking and etching steps at different depths, thereby reducing manufacturing complexity.
2Manufacturing precision
If separate steps of masking, etching and metal deposition are used to produce recesses of different depths, then multiple pinch-off voltages are achieved, but manufacturing cost increases
Solution Approach 1:
The invention changes the parameter from gate depth to gate length to achieve different pinch-off voltages. Instead of varying the depth of recesses (which requires multiple etching steps), the patent uses gates of the same depth but different lengths. This parameter substitution maintains the ability to achieve multiple pinch-off voltages while simplifying the manufacturing process to a single etching depth.
Solution Approach 2:
The invention merges multiple manufacturing operations into fewer steps. By using a single etching depth for all gates and differentiating only by gate length (which can be achieved in a single masking and etching cycle), the patent combines what would otherwise require separate masking, etching, and deposition steps into a more integrated process, thereby reducing manufacturing cost.
3Manufacturing precision
If separate steps of masking, etching and metal deposition are used to produce recesses of different depths, then multiple pinch-off voltages are achieved, but yield reduces
Solution Approach 1:
The invention changes the parameter from gate depth to gate length to achieve different pinch-off voltages. Instead of varying the depth of recesses (which requires multiple etching steps), the patent uses gates of the same depth but different lengths. This parameter substitution maintains the ability to achieve multiple pinch-off voltages while simplifying the manufacturing process to a single etching depth.
Data Source
AI summary
A compound field effect transistor having multiple pinch-off voltages, comprising first and second field effect transistors, each field effect transistor comprising a semiconductor layer, the semiconductor layer having an electrically conducting layer therein. An ohmic contact layer on the semiconductor layer, a source and a drain on the ohmic contact layer, at least one gate on the semiconductor layer between source and drain, at least one gate of the first transistor and one gate of the second transistor being matched gates, each gate having the same effective thickness of electrically conducting layer beneath it, but the gates having different gate lengths.