Compound Instruction Set Architecture for Neural Inference Chips
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Solution Overview
Problem
Current neural inference processing technologies face inefficiencies in executing complex computations due to limitations in instruction set architectures, which hinder parallelism and data path operations, leading to suboptimal performance in neural network inference tasks.
Innovation Solution
A compound instruction set architecture (ISA) is introduced that enables efficient execution of neural inference operations by updating program counters, loop counters, and address registers within each instruction, allowing for simultaneous control, address, and data operations, thereby optimizing pipeline parallelism and data path parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional instruction set architecture is used for neural inference processing, then the device complexity is reduced and ease of manufacture is improved, but the execution efficiency and productivity are degraded due to limitations in parallelism and data path operations
Solution Approach 1:
The instruction set architecture is segmented into distinct operational categories (data path operations, control operations, address operations) that can be executed in parallel. Each operation type is handled by specialized execution units, allowing simultaneous processing of multiple instruction components within a single instruction cycle, thereby improving execution efficiency without requiring a complete architectural overhaul.
Solution Approach 2:
The patent implements a universal instruction format that can represent multiple operation types (data, control, address) within a single instruction structure. This multi-functional instruction set allows the same hardware pipeline to handle diverse neural network operations (matrix multiplication, activation functions, data movement) without requiring separate specialized hardware for each operation type, balancing complexity and productivity.
2Loss of time
If loop counters and program counters are updated separately in conventional architectures, then the control logic is simpler, but the runtime efficiency is reduced due to inability to compactly represent summation loops
Solution Approach 1:
The patent merges the updating of loop counters and program counters into a single unified control operation executed atomically within each instruction cycle. This combination allows the hardware to track both loop iteration state and program counter progression simultaneously, enabling compact representation of summation loops where multiple counter updates occur together rather than requiring separate control logic stages, thus reducing runtime overhead.
Solution Approach 2:
The control operation is designed to pre-calculate and update all necessary counter values (loop counters and program counter) in advance within the same instruction cycle, before the next instruction begins execution. This preliminary updating of all counter states eliminates the need for multiple sequential counter update steps, improving runtime efficiency by ensuring all control state changes are prepared beforehand.
Data Source
AI summary
A device for controlling neural inference processor cores is provided, including a compound instruction set architecture. The device comprises an instruction memory, which comprises a plurality of instructions for controlling a neural inference processor core. Each of the plurality of instructions comprises a control operation. The device further comprises a program counter. The device further comprises at least one loop counter register. The device is adapted to execute the plurality of instructions. Executing the plurality of instructions comprises: reading an instruction from the instruction memory based on a value of the program counter; updating the at least one loop counter register according to the control operation of the instruction; and updating the program counter according to the control operation of the instruction and a value of the at least one loop counter register.