Compressed Test Patterns for FPGA Memory Reduction
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Solution Overview
Problem
Legacy test pattern storage methods in automated test equipment (ATE) are inefficient, consuming large amounts of memory and failing to scale with increasing test pattern depth and complexity, leading to limitations in parallel testing and high-density burn-in capabilities due to the need for extensive channel linking and narrow test port access.
Innovation Solution
The channel tester card compressed pattern architecture employs implicit keep, serial pattern data in compressed pages, and per-pin compression techniques to reduce memory consumption and enable high-density testing, allowing for efficient storage and distribution of test patterns across multiple digital interfaces, thereby increasing parallelism and reducing physical space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If legacy test pattern storage methods are used, then test patterns can be stored and applied, but memory consumption is excessive and the system fails to scale with increasing test pattern depth and complexity
Solution Approach 1:
The patent segments test patterns into multiple pages, where each page contains a subset of test data. This allows the test system to handle large test patterns by dividing them into manageable chunks that can be stored and accessed efficiently, enabling scaling with test pattern depth without requiring excessive memory resources.
Solution Approach 2:
The patent implements a nested structure where compressed pages are organized within a hierarchical memory architecture. The compressed test pattern data is nested within pages, which are in turn managed by the test system's memory structure. This nested organization allows efficient storage and retrieval of large test patterns while minimizing memory consumption.
2Productivity
If extensive channel linking is implemented to support high-density testing, then parallel testing capability increases, but physical space requirements and system complexity increase
Solution Approach 1:
The patent uses compressed representations of test patterns that can be replicated and distributed across multiple test channels. Instead of requiring extensive physical channel linking hardware, the compressed test data can be copied and loaded into multiple test systems, enabling parallel testing with reduced physical space requirements.
3Loss of information
If test pattern data is stored in uncompressed format, then all test data can be retained, but memory consumption increases significantly
Solution Approach 1:
The patent applies compression algorithms that change the representation parameters of test pattern data. By transforming the data from an uncompressed format to a compressed format, the system retains all necessary test information while significantly reducing memory consumption. The compression maintains data integrity and allows full test pattern depth to be preserved.
Data Source
AI summary
Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.