Compressing Instruction Queue Microprocessor
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Solution Overview
Problem
Existing microprocessor configurations face inefficiencies in translating architectural instructions to microinstructions due to unpredictable output combinations and limited buffer capacity, leading to wasted processing cycles and power consumption from re-translation and unused storage locations in the spill buffer.
Innovation Solution
A compressing instruction queue with a storage queue and redirect logic circuit that writes microinstructions sequentially without leaving unused storage locations, allowing up to P microinstructions per clock cycle to be stored and processed efficiently, reducing re-translation and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a spill buffer with fixed row capacity is used to decouple translators from RAT, then the translators can output variable numbers of microinstructions per clock cycle, but unused storage locations (holes) are created in the buffer when fewer than maximum microinstructions are stored
Solution Approach 1:
The patent implements a folded matrix structure where multiple rows of storage locations are nested in a continuous sequential array. When one row fills up, the next microinstruction automatically wraps around to the beginning of the next row, creating a nested, space-efficient storage pattern that eliminates holes and maximizes buffer utilization.
Solution Approach 2:
The patent transitions from a traditional two-dimensional row-based buffer organization to a folded sequential array that effectively adds a wraparound dimension. This allows microinstructions to flow from the end of one row to the beginning of the next row, creating a continuous storage space that eliminates unused locations while maintaining the fixed row capacity needed for RAT decoupling.
2Reliability
If architectural instructions are re-translated when microinstructions cannot be stored in the spill buffer, then buffer capacity limitations are addressed, but valuable processing cycles are wasted and additional power is consumed
Solution Approach 1:
The patent changes the effective storage capacity parameter of the spill buffer by implementing the folded matrix structure. This allows the buffer to utilize 100% of its physical storage locations, effectively increasing the usable buffer capacity without adding physical hardware, thereby preventing microinstruction overflow and eliminating the need for re-translation.
Solution Approach 2:
The patent ensures continuous utilization of buffer storage space by implementing the wraparound mechanism. As microinstructions are produced by translators, they continuously fill storage locations in sequential order, wrapping from the end of one row to the beginning of the next, ensuring that no storage location remains unused and preventing overflow conditions that would trigger re-translation.
3Productivity
If multiple translators operate in parallel to process multiple architectural instructions simultaneously, then processing throughput is improved, but the unpredictable combination of output microinstructions creates inefficiencies in buffer utilization
Solution Approach 1:
The patent implements a universal storage structure that can accommodate any combination of microinstructions from multiple translators. The folded matrix buffer and redirect logic circuit provide a multi-functional interface that handles variable numbers of microinstructions (from 0 to maximum) in any clock cycle, regardless of which translators are active, thereby supporting parallel translator operation without coordination complexity.
Data Source
AI summary
A compressing instruction queue for a microprocessor including a storage queue and a redirect logic circuit. The storage queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic circuit is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the storage queue without leaving unused storage locations and beginning at a first available storage location in the storage queue. The redirect logic circuit performs redirection and compression to eliminate empty locations or holes in the storage queue and to reduce the number of write ports interfaced with each storage location of the storage queue.