Compressive Dielectric Layer Warpage Control in 3D IC Packages

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Solution Overview

Problem

Three-dimensional integrated circuits (3D ICs) face challenges in forming through-silicon vias (TSVs) due to varying coefficients of thermal expansion (CTEs) of different elements, leading to warpage issues that can cause metal/dielectric interfacial delamination and breakage of redistribution layers, degrading the reliability and yield of package on package (PoP) structures.

Innovation Solution

A compressive dielectric layer is deposited over TSVs to counteract the tensile stress induced by CTE mismatches, reducing warpage and improving adhesion between the molding compound and TSVs, thereby enhancing the reliability of the die package by using a combination of materials like SiN with compressive stress and specific thickness to manage thermal expansion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If through-silicon vias (TSVs) are formed in three-dimensional integrated circuits, then integration density is improved, but warpage occurs due to varying coefficients of thermal expansion causing metal/dielectric interfacial delamination and redistribution layer breakage

Engineering Contradiction:

Improveintegration densityVSAvoidwarpage-induced delamination and breakage

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

A compressive stress dielectric layer is deposited over the TSVs before final packaging to pre-counteract the tensile stress that will develop during thermal cycling. This preliminary application of compressive stress prevents warpage-induced delamination and redistribution layer breakage that would otherwise occur due to CTE mismatches between different package elements

Inventive Principle:

Principle #9Preliminary anti-action

Solution Approach 2:

The patent modifies the stress state of the dielectric layer by controlling its composition and thickness to generate compressive stress. By adjusting dielectric layer parameters (material composition, thickness), the compressive stress is optimized to counterbalance the tensile stress from thermal expansion differences, thereby reducing warpage while maintaining integration density

Inventive Principle:

Principle #35Parameter changes

2Reliability

If a compressive dielectric layer is deposited over TSVs to counteract tensile stress, then warpage is reduced and adhesion is improved, but device complexity increases

Engineering Contradiction:

Improvewarpage reduction and adhesion improvementVSAvoidpackage structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The compressive stress dielectric layer serves multiple functions simultaneously: it provides electrical insulation for the TSVs, mechanically counteracts tensile stress to reduce warpage, and improves adhesion between the molding compound and TSVs. By combining these functions into a single layer, the patent reduces overall package complexity despite adding functionality

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The compressive dielectric layer effectively reduces warpage and improves adhesion between the molding compound and TSVs, enhancing the reliability and yield of 3D ICs by minimizing stress and preventing RDL breakage.

Implementation Method 1

A compressive dielectric layer is deposited over TSVs to counteract the tensile stress induced by CTE mismatches, reducing warpage

Methodology Applied

Scientific EffectCompressive stress:

Implementation Method 2

varying coefficients of thermal expansion (CTEs) of different elements, leading to warpage issues

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 3

improving adhesion between the molding compound and TSVs, thereby enhancing the reliability of the die package

Methodology Applied

Scientific EffectAdhesion: Adhesive

Data Source

PatentUS10134706B2Warpage control of semiconductor die package

Publication Date: 2018.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved.