Compressive Interlayer for Semiconductor Metallization Stress
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Solution Overview
Problem
Thick and stiff metallization stacks in semiconductor devices cause high stresses due to thermal expansion mismatch, leading to cracks in brittle layers during temperature changes, which existing solutions attempt to mitigate by reducing temperature budgets or using less stiff metals, limiting technology and causing adverse effects.
Innovation Solution
A structured interlayer with compressive residual stress is implemented, extending beyond the metallization edges by at least 0.5 microns, counteracting tensile stresses and reducing crack probability without altering the temperature profile or metallization properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If thick and stiff metallization stacks are used to enable interconnect solutions or improve thermal performance, then thermal performance and interconnect capability are improved, but high stresses occur near film-terminating free-edges due to CTE mismatch, leading to cracks in underlying brittle layers
Solution Approach 1:
A compliant interlayer is introduced between the stiff metallization stack and the brittle underlying layers. This interlayer acts as a stress-absorbing intermediary that decouples the metallization edges from the brittle substrate, preventing crack propagation while maintaining the thermal and electrical functionality of the thick metallization structure.
Solution Approach 2:
The patent modifies the mechanical properties of the interlayer by selecting materials with specific compliance characteristics and controlling deposition parameters to achieve desired stress states. The interlayer is designed with specific thickness and material composition to optimize its ability to absorb thermal stresses generated by CTE mismatch during temperature cycling.
2Reliability
If temperature budget is reduced after deposition of the metal to avoid cracks, then crack occurrence is reduced, but technology is severely limited and adverse side effects occur
Solution Approach 1:
The compliant interlayer is prepared in advance during the deposition process, establishing a stress-management mechanism before subsequent high-temperature processing steps. This preliminary structural preparation enables the device to withstand higher temperature budgets and more aggressive processing conditions without cracking, thereby restoring technology flexibility.
3Reliability
If metals with reduced stiffness are used to avoid cracks, then crack resistance is improved, but technology is severely limited and adverse side effects occur
Solution Approach 1:
The patent segments the metallization structure into multiple functional layers: a stiff conductive metal layer for electrical connectivity and thermal management, and a separate compliant interlayer for stress absorption. This segmentation allows each layer to perform its specialized function optimally - the metal provides strength and conductivity, while the interlayer provides crack resistance.
4Reliability
If the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns, then crack propagation is prevented, but device complexity increases
Solution Approach 1:
The interlayer is designed with spatially varying geometry - it extends beyond the metallization edges specifically at locations where cracks are most likely to initiate and propagate. This local extension provides targeted crack-stop functionality without requiring the entire interlayer structure to be more complex, maintaining simplicity in regions where it is not needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structured interlayer effectively decouples metallization edges from the substrate, reducing peak stress and preventing cracks by spreading tensile stress, thus enhancing the fracture strength of brittle materials under compression.
Implementation Method 1
The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer
Implementation Method 2
The structured interlayer effectively decouples metallization edges from the substrate, reducing peak stress and preventing cracks by spreading tensile stress
Implementation Method 3
The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer
Data Source
AI summary
A semiconductor device includes a substrate, a structured interlayer on the substrate and having a defined edge, and a structured metallization on the structured interlayer and also having a defined edge. The defined edge of the structured interlayer faces the same direction as the defined edge of the structured metallization. The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.