Compute Circuit DVFS Using Accelerator Power State Indications
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Solution Overview
Problem
Compute processing devices in datacenter environments consume unnecessary power due to operating at a fixed clock frequency regardless of the number of interrupts received, leading to inefficiencies in power management.
Innovation Solution
Implement a power management system where an accelerator circuit communicates power state indications to a compute circuit, allowing for dynamic voltage and frequency scaling (DVFS) to adjust power consumption based on workload demands, using power management interface circuits and power management techniques to switch between high and low power states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the compute circuit operates at a fixed clock frequency to ensure consistent processing performance, then processing reliability is maintained, but power consumption increases unnecessarily during low-workload periods
Solution Approach 1:
The compute circuit transitions from a static fixed-frequency operation to dynamic frequency scaling. The clock frequency is adjusted based on workload conditions - operating at higher frequencies during high-interrupt periods and lower frequencies during low-interrupt periods, thereby matching processing capability to actual demand while maintaining reliability
Solution Approach 2:
The system changes the operational parameters of the compute circuit by dynamically adjusting the clock frequency and supply voltage. These parameter changes allow the circuit to adapt its power consumption characteristics to workload conditions while maintaining adequate processing performance when needed
2Productivity
If the compute circuit operates at high clock frequency to handle peak workload demands, then processing speed is improved, but power consumption increases continuously even during low-workload periods
Solution Approach 1:
The compute circuit implements dynamic frequency scaling where the clock frequency varies according to workload intensity. During peak demands, the frequency increases to maintain high processing speed; during low-workload periods, the frequency decreases to reduce power consumption, eliminating the need to operate continuously at maximum frequency
3Use of energy by moving object
If dynamic voltage and frequency scaling is implemented to reduce power consumption, then power efficiency is improved, but system complexity increases due to additional power management circuits and control logic
Solution Approach 1:
The power management system operates autonomously by monitoring interrupt conditions and automatically adjusting the compute circuit's frequency and voltage without requiring external control. The system serves itself by detecting workload changes and independently making power management decisions, reducing the need for complex external control mechanisms
Data Source
AI summary
A circuit system includes an accelerator circuit and a compute circuit. The accelerator circuit generates a request in response to receiving packets of data. The accelerator circuit generates an indication of a low power state based on a reduced number of the packets of data being received. The compute circuit performs a processing operation for the accelerator circuit using the packets of data in response to receiving the request. The compute circuit comprises a power management circuit that decreases a supply voltage in the compute circuit and decreases a frequency of a clock signal in the compute circuit in response to the indication of the low power state from the accelerator circuit.