Compute-in-Memory Bitcell Reducing Power and Leakage
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Solution Overview
Problem
In computation-intensive applications like machine learning, the data flow between memory and processing units in traditional Von Neumann architectures becomes a bottleneck, hindering processing speed.
Innovation Solution
A compute-in-memory storage cell design featuring cross-coupled inverters, capacitors, and transistors that allow for in-memory data processing by charging and discharging capacitors based on input and stored bits, enabling efficient multiplication and accumulation operations without the need for full rail transmission gates or boosted word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional Von Neumann architecture is used for data processing, then data can be stored in memory, but data movement between memory and processing units becomes a bottleneck for processing speed
Solution Approach 1:
The patent merges memory storage and computation functions into a single integrated structure. The compute-in-memory bitcell combines SRAM storage elements with logic gates (AND, OR, XOR) and capacitors, allowing data to be processed in place without movement between separate memory and processing units, thereby eliminating the data movement bottleneck
Solution Approach 2:
The bitcell design provides multi-functionality by enabling both data storage and various logic operations within the same cell structure. The cross-coupled inverters provide storage while logic gates perform computation, and capacitors enable analog computation functions, making the cell universally applicable for both memory and processing tasks
2Reliability
If full rail transmission gates are used for bit manipulation, then complete logic operations can be performed, but power consumption and leakage increase
Solution Approach 1:
The patent changes the operating parameters by using partial charging of capacitors instead of full rail voltage switching. The capacitors are charged to intermediate voltage levels proportional to the logic operation results, reducing the energy required for bit manipulation while maintaining logic operation accuracy through controlled voltage levels
Solution Approach 2:
Instead of using full rail transmission gates that switch between complete voltage rails, the invention employs partial charging actions where capacitors are charged only to the extent needed to represent logic states. This partial action reduces power consumption and leakage while still achieving reliable logic operations
3Extent of automation
If boosted word lines are used for computing operations, then computation can be performed, but die space requirements increase
Solution Approach 1:
The invention merges the word line function with the bitcell structure itself. The word line connects directly to the gates of pass transistors within each bitcell, eliminating the need for separate boosted word line structures. This integration reduces die space while maintaining full computation capability through the embedded logic gates and capacitors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces power consumption and leakage while maintaining full-rail charging, allowing for efficient in-memory computation with minimal variation in linearity, thereby enhancing processing speed and reducing die space requirements.
Implementation Method 1
a capacitor having a first plate connected to the read bit line; and a first pass transistor connected between the first output node and a second plate of the capacitor
Data Source
AI summary
A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.