Compute-In-Memory Booth Circuit for Signed Data Without 2's Complement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing compute-in-memory (CIM) circuits require additional 2's complement circuits for processing signed data, which complicates the design and increases the size of the circuit, making them unsatisfactory for certain applications.
Innovation Solution
The CIM circuit performs in-memory computations on signed input and weight data elements without 2's complement conversion by using a Booth encoder, Booth decoder, and sign-aware multiplexers to determine whether to forward or invert Booth encoded values based on the signs of the data elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 2's complement circuits are added to process signed data in CIM circuits, then the computational capability for signed data is improved, but the circuit complexity and size increase
Solution Approach 1:
The patent extracts the 2's complement conversion function from the traditional separate preprocessing stage and integrates it directly into the memory array computation process. By performing sign extension and 2's complement conversion in-place during the multiply-accumulate operation, the design eliminates the need for additional dedicated 2's complement circuits, thereby reducing overall circuit complexity while maintaining full signed data processing capability
Solution Approach 2:
The patent merges multiple functions (sign detection, sign extension, 2's complement conversion, and multiply-accumulate computation) into a single integrated memory array operation. The computation circuit performs these operations simultaneously during the MAC process, combining what were traditionally separate circuit blocks into one unified structure, thus reducing device complexity without sacrificing computational versatility
2Adaptability or versatility
If 2's complement circuits are added to process signed data, then the ability to handle signed input and weight data is improved, but the overall circuit size increases
Solution Approach 1:
The patent transitions from a sequential multi-stage processing approach (requiring separate 2's complement circuits before MAC operations) to a parallel in-place computation approach within the memory array. By utilizing the vertical stacking of memory cells and conductors in the 3D memory architecture, the design performs sign extension and 2's complement conversion along the vertical dimension during the same time period as the MAC computation, effectively reducing the horizontal circuit footprint
3Measurement precision
If additional circuits are added for signed data processing, then the computational accuracy for signed data is improved, but the design complexity increases
Solution Approach 1:
The patent implements self-service computation where the memory array itself performs the 2's complement conversion and sign extension operations that were traditionally required by external preprocessing circuits. The computation circuit uses the inherent structure of the memory array (conductors, transistors, and storage nodes) to automatically perform these mathematical operations as part of the normal MAC process, eliminating the need for additional design complexity while maintaining computational accuracy
Data Source
AI summary
A memory circuit includes a Booth encoder configured to receive a first data element including a first sign portion and a first data portion. The memory circuit includes a Booth decoder configured to receive a second data element including a second sign portion and a second data portion, and provide a product based on the first data element and the second data element. The memory circuit includes a plurality of multiplexers operatively coupled between the Booth encoder and the Booth decoder. The plurality of multiplexers are configured to receive a plurality of encoded signals from the Booth encoder and to change respective logic states of the plurality of encoded signals based on the first sign portion and the second sign portion, causing the Booth decoder to provide the product.