Compute-in-Memory Circuits With Shared Adder Trees for Faster Updates
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Solution Overview
Problem
Conventional digital computing-in-memory (dCIM) systems face challenges with large layout area due to numerous adder trees and slow performance due to long download times of memory content, necessitating improvements in multiply-and-accumulate operations.
Innovation Solution
A compute-in-memory circuit design that utilizes tri-state NOR gates and pipelined adder trees, allowing sharing of adder trees among subgroups and enabling simultaneous multiplication and accumulation operations, reducing layout area and download time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate adder trees are provided for each subgroup, then multiplication and accumulation operations can be performed independently, but the layout area becomes excessively large
Solution Approach 1:
Multiple subgroups share a common adder tree structure. The adder tree is designed to accept inputs from multiple subgroups through time-multiplexed connections, allowing one adder tree to serve multiple subgroups sequentially, thereby reducing the total number of adder trees and layout area.
Solution Approach 2:
The adder tree inputs are dynamically configured through tri-state buffers that enable different subgroups to connect to the adder tree at different times. This dynamic switching allows a single adder tree to process operations from multiple subgroups in sequence, maintaining operational independence while sharing hardware resources.
2Reliability
If all word lines are toggled to download memory content, then complete weight updates can be performed, but the download time becomes excessively long
Solution Approach 1:
The memory array is divided into multiple subgroups, each with its own word lines. This segmentation allows selective activation of only the word lines corresponding to the subgroup being updated, rather than toggling all word lines in the entire memory array, thereby reducing download time while maintaining complete weight updates for the active subgroup.
Solution Approach 2:
Weight updates are performed in advance for specific subgroups before they are needed for computation. By pre-loading weights into subgroups that will be activated next, the system minimizes idle time and ensures that complete weight updates are ready when computation begins, reducing overall download time.
3Reliability
If multiplication operations are stopped during content download, then memory updates can be performed, but system performance degrades
Solution Approach 1:
While one subgroup is undergoing weight updates, other subgroups continue to perform multiplication operations. The system maintains continuous useful computation by parallelizing updates and operations across different subgroups, ensuring that multiplication operations are not globally stopped during content download, thereby preserving system performance.
Solution Approach 2:
The system dynamically switches between subgroups, allowing some subgroups to be in update mode while others are in computation mode. This dynamic state management enables memory updates and multiplication operations to coexist in different parts of the system simultaneously, maintaining overall productivity while ensuring reliable weight updates.
Data Source
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AI summary
A compute-in-memory circuit is provided. The circuit includes one or more input lines receiving M input data elements, M being greater than zero, an array of memory cells including one or more subgroups, each subgroup of the one or more subgroups storing M stored data elements, multiplier circuits connected to the array of memory cells and to the one or more input lines, and configured to multiply the M input data elements by the M stored data elements in a selected subgroup of the one or more subgroups and configured to provide a multiplier output having M data elements, and accumulation circuitry including an accumulator input of M data elements connected to the multiplier output and configured to generate a sum of the M data elements of the multiplier output, wherein the multiplier circuits supply a multiplication result to the multiplier output from subgroups.