Concave Floating Gate Profile for Flash Memory Coupling Ratio
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current flash memory devices face challenges in achieving optimal coupling ratios and performance due to limitations in floating gate design, particularly with polysilicon floating gates, which affect data retention and programming speed.
Innovation Solution
The manufacturing process involves forming a floating gate with a concave sidewall and a specific dielectric structure, including control gates, spacer structures, and erase gates, to enhance coupling ratios without thinning the dielectric layers or increasing the floating gate thickness, thereby improving memory device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dielectric layer thickness is reduced to improve coupling ratio, then the coupling ratio between floating gate and erase gate is improved, but the reliability of the dielectric layer deteriorates due to increased electric field stress and potential breakdown
Solution Approach 1:
The patent employs a composite dielectric structure consisting of multiple layers with different materials (first dielectric layer, second dielectric layer, third dielectric layer) having different dielectric constants. This composite approach allows optimization of the coupling ratio while maintaining adequate thickness to prevent breakdown, as each layer can be tailored for specific electrical and mechanical properties.
Solution Approach 2:
The patent applies different dielectric materials at different locations between the floating gate and erase gate. The first dielectric layer has a first dielectric constant, the second dielectric layer has a second dielectric constant, and the third dielectric layer has a third dielectric constant, creating local variations in electrical properties to optimize both coupling ratio and reliability in different regions of the structure.
2Duration of action of moving object
If the floating gate thickness is increased to improve data retention, then the data retention is improved, but the programming speed deteriorates due to increased charge injection time
Solution Approach 1:
The patent uses a composite dielectric structure with multiple layers having different dielectric constants positioned between the floating gate and erase gate. This configuration enhances the coupling ratio, which improves charge injection efficiency during programming, thereby maintaining fast programming speeds even when the floating gate thickness is increased for better data retention.
Data Source
AI summary
A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.