Concave Via Interconnect Geometry for Compact Package Power Delivery
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Solution Overview
Problem
There is a need to improve the performance of integrated devices and packages while maintaining a small form factor, particularly in terms of current carrying capacity and thermal conductivity, which is not adequately addressed by existing technologies.
Innovation Solution
The use of via interconnects with a planar cross-sectional shape that includes a concave portion, which increases the size of the cross section while maintaining the same minimum spacing and pitch, thereby enhancing current carrying capacity and thermal conductivity without increasing the overall size of the substrate or package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If via interconnects with traditional circular cross section are used, then the substrate size can be kept small, but the current carrying capacity and thermal conductivity are limited
Solution Approach 1:
The patent applies asymmetry by transitioning from traditional circular via interconnects to non-circular cross-sectional shapes (such as rectangular, square, or other polygonal forms). This asymmetric geometric change allows the via interconnects to achieve larger cross-sectional areas and better aspect ratios within the same pitch constraints, thereby increasing current carrying capacity and thermal conductivity without proportionally increasing substrate size. The non-circular geometry optimizes the distribution of current and heat flow paths.
Solution Approach 2:
The patent utilizes dimensionality change by optimizing the via interconnect geometry in the planar cross-sectional dimension rather than simply increasing depth. By changing from circular to non-circular cross-sections, the design exploits the two-dimensional space more efficiently, achieving larger effective conduction areas within the same lateral footprint. This dimensional optimization allows increased current and thermal conduction capacity without linearly increasing the substrate's overall area.
2Productivity
If the number of interconnects is increased to improve performance, then electrical functionality is enhanced, but the substrate size and complexity increase
Solution Approach 1:
The patent applies parameter changes by modifying the geometric parameters of via interconnects from circular to non-circular cross-sections. This parameter transformation enables increased current carrying capacity and thermal conductivity per via interconnect, allowing the substrate to achieve higher overall performance with the same number of interconnects. Alternatively, it enables the same performance level with fewer interconnects, thereby reducing substrate complexity and interconnect density requirements.
3Quantity of substance
If via interconnects with larger cross section are used, then current carrying capacity improves, but the pitch and spacing requirements increase
Solution Approach 1:
The patent resolves this contradiction by employing asymmetric non-circular via interconnect geometries that optimize the relationship between cross-sectional area and lateral footprint. Shapes such as rectangles or squares with optimized aspect ratios provide larger cross-sectional areas for current conduction while maintaining compact lateral dimensions. This asymmetric geometry allows larger effective conduction areas without proportionally increasing the pitch between adjacent via interconnects, as the non-circular shapes utilize space more efficiently than circular designs.
Data Source
AI summary
A package comprising an integrated device and a substrate coupled to the integrated device, wherein the substrate comprises a plurality of via interconnects, and wherein at least one via interconnect from the plurality of via interconnects comprises a planar cross sectional shape that includes a concave portion.