Concentric Through Electrodes for High-Density Semiconductor Interconnects
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Solution Overview
Problem
Conventional semiconductor devices face challenges in miniaturization due to the large area required for through electrodes, increased parasitic capacitance, and difficulty in achieving high density and low parasitic capacitance, which affects chip size, reliability, and efficiency.
Innovation Solution
A semiconductor device configuration featuring a solid plug-shaped first electrical conductor and a pipe-shaped second electrical conductor surrounding it, both extending through the semiconductor substrate with an insulating film for electrical insulation, allowing multiple through electrodes in one hole and reducing area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional through electrodes are used with one electrode per through hole, then electrical conduction between front and back sides is achieved, but the area required for through electrodes becomes large, preventing chip miniaturization
Solution Approach 1:
The patent merges multiple through electrodes into a single through hole by forming multiple electrical conductors (first electrical conductor and second electrical conductor) within the same through hole. This combining approach reduces the number of through holes needed while maintaining reliable electrical conduction, thereby minimizing the area occupied by through electrodes and enabling chip miniaturization.
Solution Approach 2:
The patent implements a nested structure where the first electrical conductor and second electrical conductor are arranged concentrically within the same through hole, with the insulating film positioned between them. This nesting configuration allows multiple electrical conductors to coexist in a compact space, significantly reducing the area required for through electrodes while ensuring proper electrical insulation and maintaining conduction reliability.
2Productivity
If multiple through electrodes are provided to achieve high density, then connection density increases, but the area occupied by through electrodes increases, affecting chip size
Solution Approach 1:
The patent combines multiple through electrodes into one through hole, allowing high connection density to be achieved without proportionally increasing the area occupied. By providing multiple electrical conductors within a single through hole, the patent enables more connections per unit area, thereby increasing productivity while minimizing area consumption.
Solution Approach 2:
The patent transitions from a two-dimensional arrangement where each through electrode occupies separate planar space to a three-dimensional configuration where multiple electrical conductors are stacked concentrically within the same through hole. This dimensional change allows multiple connections to be made in the vertical dimension rather than spreading out horizontally, achieving high density without increasing area.
3Ease of manufacture
If conventional through electrode structures are used, then manufacturing is simplified, but parasitic capacitance increases, affecting device performance
Solution Approach 1:
The patent introduces an insulating film as an intermediary between the first electrical conductor and the second electrical conductor. This insulating film acts as a mediator that electrically isolates the two conductors, preventing parasitic capacitance formation between them while still allowing both conductors to be formed within the same through hole using a unified manufacturing process, thus maintaining manufacturing simplicity.
4Reliability
If through electrodes are provided with adequate spacing for reliability, then connection reliability is maintained, but the area required increases, preventing miniaturization
Solution Approach 1:
The patent uses a nested configuration where the first electrical conductor and second electrical conductor are positioned concentrically within the same through hole, separated by an insulating film. This nesting arrangement ensures proper electrical isolation and maintains connection reliability without requiring additional spacing between separate through holes, thereby minimizing the area required for through electrodes and enabling chip miniaturization.
Data Source
AI summary
A semiconductor device 100 is provided with a multiplex through plug 111 that fills an opening extending through the silicon substrate 101. The multiplex through plugs 111 comprises a column-shaped and solid first through electrode 103, a first insulating film 105 that covers the cylindrical face of the first through electrode 103, a second through electrode 107 that covers the cylindrical face of the first insulating film 105 and a second insulating film 109 that covers the cylindrical face of the second through electrode 107, and these have a common central axis. The upper cross sections of the first insulating film 105, the second through electrode 107 and the second insulating film 109 are annular-shaped.