Concurrent Emulation Debug Environment for SoC Verification
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Solution Overview
Problem
Existing hardware emulation systems face limitations in partitioning capacity, leading to significant unused capacity and inefficiencies in emulating smaller sub-portions of circuit designs, particularly in system-on-a-chip (SoC) verification, where bugs in hardware components are often discovered during software verification due to incomplete design cycles.
Innovation Solution
A concurrent emulation debug environment is introduced, comprising an emulator, an emulation control station with model compaction, an emulation trace module, and a model state module, which combines multiple design models into a single combined model, captures logical values, and stores states for debugging, enabling efficient debugging of electronic designs concurrently emulated on a single emulator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If emulator capacity is partitioned into smaller sections, then utilization efficiency is improved, but device complexity increases
Solution Approach 1:
The emulator capacity is segmented into multiple partitions that can be independently allocated to different design models. Each partition represents a manageable unit of emulator resources, allowing flexible allocation while maintaining overall system control. The segmentation enables multiple users to simultaneously utilize different portions of the emulator capacity without interfering with each other.
Solution Approach 2:
The partition management system is designed to handle multiple functions: allocating emulator capacity to different design models, managing multiple users simultaneously, tracking resource usage, and enabling dynamic reconfiguration. This universal partition management approach eliminates the need for separate management mechanisms for each function, reducing overall system complexity while improving utilization.
2Device complexity
If partitioning is restricted to board level, then device complexity is reduced, but emulator capacity utilization deteriorates
Solution Approach 1:
The emulator capacity is segmented into fine-grained units that are smaller than traditional board-level partitions. This allows sub-portions of circuit designs to be allocated precisely to match the actual resource requirements, eliminating wasted capacity. The segmentation enables allocation at the level of individual design components rather than forcing entire boards to be allocated or unallocated as single units.
Solution Approach 2:
Different regions of the emulator capacity are allocated with different granularities based on local requirements. Critical areas that need fine control are segmented into smaller units, while less critical areas can use coarser granularity. This local quality approach optimizes the balance between management complexity and utilization efficiency for different parts of the emulator.
3Productivity
If multiple design models are emulated concurrently, then productivity is improved, but debugging difficulty increases
Solution Approach 1:
The debugging system is segmented to provide independent debug capabilities for each design model being emulated concurrently. Each design model has its own debug interface and control mechanisms, allowing engineers to debug individual models without interference from other models. The segmentation is transparent to the user, who experiences a simple interface despite the complex concurrent emulation occurring behind the scenes.
Data Source
AI summary
Technologies for debugging hardware errors discovered during hardware assisted software verification processes are provided. For example, in one embodiment, a concurrent emulation debug environment including a concurrent emulation system, an emulation trace module and a model state module is provided. The concurrent emulation system includes an emulator and an emulation control station configured to allow simultaneous emulation of multiple electronic designs. The model state module is configured to record the state of the electronic designs during emulation and the emulation trace module is configured to capture trace data associated with the emulation. A backup and capture module is also disclosed that is configured to store the recorded state and the captured trace data for use during a hardware debug process.