Concurrent Memory Access via Section Independence
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Solution Overview
Problem
Ferroelectric RAM (FeRAM) devices face increased access times due to high voltages required for polarization, leading to bifurcated writeback operations that prolong data writing and consume more power, which is inefficient compared to volatile RAM.
Innovation Solution
Implementing a method for concurrent access to independent sections of a memory array, where a second memory cell can be activated during the precharge operation of the first memory cell, utilizing latching hardware to manage read addresses and selecting appropriate delay times based on section independence, allowing for enhanced write operations and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied to polarize ferroelectric memory cells, then non-volatile storage capability is achieved, but access time increases and power consumption increases
Solution Approach 1:
The memory array is divided into multiple independent sections, each with its own precharge circuit. This segmentation allows different sections to operate independently and concurrently, enabling the controller to access one section while another section is being precharged, thereby reducing overall access time without compromising the non-volatile storage capability of ferroelectric cells.
Solution Approach 2:
The precharge circuit performs preliminary charging of the plate voltage before the actual read or write operation. By initiating this precharging action in advance during idle periods or concurrent operations, the system prepares the memory cells for subsequent high-voltage polarization operations, reducing the effective access time required for data operations.
2Use of energy by stationary object
If bifurcated writeback operation is used to mitigate high voltage, then power consumption is reduced, but write operation time increases
Solution Approach 1:
The writeback operation is divided into two separate phases: first writing logical zeros when plate voltage is high, then writing logical ones when plate voltage is low. This segmentation of the write operation allows the system to complete writeback without requiring sustained high voltage, reducing power consumption while managing the extended write time through efficient phase separation.
Solution Approach 2:
The writeback operation alternates between two voltage states in a periodic manner - high voltage phase for writing zeros, then low voltage phase for writing ones. This periodic action pattern allows the system to complete the writeback operation using pulsed high voltage rather than continuous high voltage, reducing overall power consumption while systematically completing both write operations.
3Speed
If concurrent access to independent sections is implemented, then access speed is improved, but device complexity increases
Solution Approach 1:
The memory device is segmented into multiple independent sections, each with dedicated precharge circuits and control logic. This segmentation enables concurrent access to different sections, improving overall access speed. The complexity is managed by replicating proven circuit designs across sections rather than creating complex inter-dependent circuits.
Solution Approach 2:
Each memory section is designed with universal, identical circuitry including precharge circuits, sense amplifiers, and control logic. This multi-functionality approach allows the same circuit design to serve multiple sections, improving access speed through concurrency while minimizing device complexity by avoiding custom designs for each section. The controller universally manages all sections using the same control protocols.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster and more efficient memory access by allowing concurrent operations across independent memory sections, reducing the time required for write operations and lowering power consumption, thus improving the performance and efficiency of FeRAM devices.
Implementation Method 1
FeRAM devices may use similar device architectures as volatile memory but may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device
Implementation Method 2
a precharge circuit associated with the first subarray to precharge a plate voltage for the first subarray
Implementation Method 3
concurrently performing a first operation at a first memory cell and a second operation at a second memory cell
Data Source
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AI summary
A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.