Concurrent Timing Budgeting for Nested IC Partitions
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Solution Overview
Problem
Current design methodologies for integrated circuits face challenges in efficiently managing timing budgets, especially in nested partitions, leading to complex and time-consuming processes due to the need for manual intervention and repetitive iterations, which hinders rapid turnaround times and scalability in giga-gate chip designs.
Innovation Solution
A method for concurrent generation of timing budgets across multiple levels of hierarchy in integrated circuit designs, allowing for simultaneous timing budgeting of all partitions at each level, reducing the time spent on generating budgets and enabling faster design closure with minimal manual intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual timing budgeting is performed for each partition sequentially, then timing accuracy can be ensured, but the design closure time increases significantly
Solution Approach 1:
The patent segments the timing budgeting process into hierarchical levels (top-level chip, partition-level, and sub-partition level). Each level has its own timing constraints that are derived from the parent level, allowing parallel processing while maintaining timing accuracy through hierarchical constraint propagation
Solution Approach 2:
The patent performs preliminary timing budgeting at the top-level chip before partitioning. This preliminary action establishes global timing constraints that guide subsequent partition-level budgeting, reducing the need for iterative adjustments and manual intervention in later stages
2Device complexity
If the design is divided into multiple hierarchical partitions, then the complexity of timing analysis is reduced, but the process requires repetitive iterations and manual intervention
Solution Approach 1:
The patent implements automated feedback loops where timing violations detected at any hierarchical level automatically trigger constraint adjustments and re-analysis. This feedback mechanism eliminates manual intervention by systematically identifying and resolving timing issues through algorithmic constraint propagation and violation detection
Solution Approach 2:
The patent creates a universal timing budgeting framework that operates across all hierarchical levels with consistent algorithms and constraint handling. This multi-functional approach allows the same automated processes to handle top-level chip timing, partition timing, and sub-partition timing uniformly, reducing the need for level-specific manual adjustments
3Productivity
If concurrent timing budgeting is performed for all partitions, then design closure time is reduced, but coordination between nested partitions becomes complex
Solution Approach 1:
The patent applies nested doll principle by embedding timing constraints within hierarchical levels. Each partition contains nested timing constraints from parent levels, and sub-partitions contain constraints from their parent partitions. This nesting structure allows concurrent execution at all levels while automatically maintaining coordination through the hierarchical constraint hierarchy
Solution Approach 2:
The patent adds a hierarchical dimension to the timing budgeting process. Instead of coordinating partitions in a single dimension, the system organizes them across multiple hierarchical dimensions (chip level, partition level, sub-partition level). This dimensional organization allows concurrent processing while automatically managing coordination through the hierarchical structure
Data Source
AI summary
In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.