Conditional Construct Splitting for GPU Latency Hiding

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-latency instructions in conditional constructs within software compiled for graphics processing units (GPUs) cause significant delays due to stalling, as dependent instructions wait for the completion of high-latency operations, leading to inefficiencies in workload execution.

Innovation Solution

A compiler optimization technique called conditional construct splitting, where high-latency conditional constructs are split into two separate constructs, allowing independent instructions to execute in parallel with the high-latency operation, thereby mitigating the latency stall by inserting non-dependent instructions between the split constructs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conditional constructs include high-latency instructions and dependent instructions, then the correctness of data dependency is maintained, but execution time increases significantly due to stalling

Engineering Contradiction:
Improvedata dependency correctnessVSAvoidexecution time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides a single conditional construct containing high-latency instructions into multiple separate conditional constructs. By segmenting the original construct, the compiler can insert independent instructions between the segmented parts, allowing parallel execution during high-latency operations while maintaining data dependency correctness through preserved conditional expressions and inserted synchronization instructions.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If instructions are executed sequentially in conditional constructs, then simplicity of execution flow is maintained, but productivity decreases due to idle cycles during high-latency operations

Engineering Contradiction:
Improveexecution flow simplicityVSAvoidthroughput
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent transforms the static sequential execution flow into a dynamic structure where independent instructions can execute in parallel with high-latency operations. The compiler dynamically analyzes data dependencies to identify independent instructions that can be executed concurrently, thereby improving throughput while maintaining manageable execution flow through systematic insertion points.

Inventive Principle:
Principle #15Dynamics

3Loss of time

If the compiler optimizes by splitting conditional constructs, then latency is hidden through parallel execution, but device complexity increases due to multiple conditional constructs

Engineering Contradiction:
Improvelatency stallVSAvoidconditional construct structure
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent uses inserted independent instructions as intermediaries between segmented conditional constructs. These intermediary instructions serve as placeholders that enable parallel execution during high-latency operations while maintaining the logical flow of the original program. The compiler systematically identifies and inserts these intermediaries at optimal points to hide latency without creating excessive structural complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10740074B2Conditional construct splitting for latency hiding
Publication Date: 2020.08.11 ADVANCED MICRO DEVICES INC
  • US10740074B2 patent drawing
  • US10740074B2 patent drawing
  • US10740074B2 patent drawing

AI summary

A method and system for compiler optimization includes analyzing a representation of source code to identify an original conditional construct having both a high-latency instruction and one or more instructions dependent on the high-latency instruction in a branch of the conditional construct. A set of one or more instructions following the conditional construct in the representation of source code and independent of the high-latency instruction is selected. An optimized representation of the source code is generated, whereby the optimized representation replaces the original conditional construct with a first split conditional construct positioned prior to the selected set of one or more instructions and a second split conditional construct positioned following the selected set of one or more instructions, The method further includes generating an executable representation of the source code based on the optimized representation of the source code.