Processor Architectures/Configuration TRIZ Cases
- Beam Tracing Intersection Query for Bounding Volume Hierarchy
A beam tracing method calculates intersection parameters against axis-aligned bounding boxes to determine query beam overlap with target volumes.
- Shadow Map Rotation for Sub-Frame Accumulation
Rotating frustum views across multiple subframes averages noise and jagged artifacts without compromising precision.
- Modular Pipeline Shader Configuration for Programmability
A modular pipeline system configures shaders in user-defined sequences to enable flexible execution patterns.
- Unified Graphics Pipeline Rendering Mixed Primitives
A unified graphics pipeline renders diverse primitive and tessellation domain types within a single draw call command.
- GPU-CPU Image Encoding Segmentation for Processing Bottlenecks
A GPU removes spatial redundancy from image blocks and generates specifying information to guide CPU compression processing.
- Ray Packet Processing for SIMD Ray Tracing Coherency
Segmenting rays into k-ray packets maintains coherency for secondary rays, resolving performance degradation in SIMD ray tracing.
- Convolution Operator Sub-Multipliers for Mixed-Precision Neural Networks
Decomposing convolution multipliers into sub-multipliers processes mixed-precision operands in parallel, reducing computational energy consumption.
- Polar Stroking for Vector Graphics GPU Rendering
Polar stroking evaluates tangent angle changes to generate tessellated paths, eliminating CPU pre-processing bottlenecks and reducing memory usage.
- Conditional Construct Splitting for GPU Latency Hiding
Splitting conditional constructs allows independent instructions to execute during high-latency stalls, reducing execution time.
- Texture Coordinate Generator Eliminates Division for Non-Power-of-2 Maps
A texture coordinate generator computes final coordinates using multiplication and addition operations.
- Reconfigurable I/O Module Board for Adaptable Graphics Systems
A reconfigurable I/O module board connects to a graphics processor via a dual compression connector.
- Coalescing Graphics Operations for Parallel Processing Efficiency
Merging separate graphics tasks into unified operations resolves serial processing bottlenecks while managing thread synchronization complexity.
- Method Macro Expander for GPU Work Packet Processing
A method macro expander receives work packets from a driver and executes commands to generate expanded packets for the graphics processing unit pipeline.
- Dynamic Frame Rate Adjustment for Thermal Management
A computing device adjusts target frame rates based on gameplay states to conserve battery power and thermal headroom.
- Tile-Based Graphics Pipeline Bandwidth Optimization
A tile-based graphics processing pipeline stores and reuses sampling position values across adjacent tiles to reduce external memory transactions.
- Reconfigurable 3D Graphics Processor Pipeline Mode Switching
A reconfigurable 3D graphics processor pipeline switches between direct rasterizing and tiling modes to optimize external memory bandwidth usage.
- Daisy Chain Inference Devices for Object Identification
Segmented inference devices in a daisy chain resolve object identification limits across diverse data sources while managing system complexity.
- Display Resource Scheduling for Embedded Systems
A display resource scheduling method prioritizes a hardware accelerator over a graphics processing unit.
- Graphics Effect Data Structure Decoupling Shaders
An effect processing system stores a data structure describing graphics effects implemented by multiple passes and shader code modules.
- Dynamic Task Scheduling for In-Vehicle Image Processing
An image processing apparatus estimates task completion times to schedule parallel execution units efficiently.
- Position-Based Rendering for Multi-Die GPU Scalability
A position-based rendering apparatus partitions graphics workloads across multiple silicon dies to boost processing throughput.
- Interruptible GPU Context Switching via Precise Position Tracking
An interruptible GPU saves and restores processing contexts to memory for seamless task switching.