Dynamic Task Scheduling for In-Vehicle Image Processing
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Solution Overview
Problem
In multi-processor systems, existing scheduling methods face inefficiencies between strict real-time and pseudo real-time scheduling, where strict real-time ensures performance but decreases processor efficiency, while pseudo real-time improves efficiency but lacks performance assurance, especially when task loads are unevenly distributed.
Innovation Solution
An image processing apparatus that estimates task completion time in each processing unit based on decoding or encoding parameters, allowing for dynamic scheduling to ensure tasks are executed efficiently and within target completion times, even when task loads are biased.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strict real-time scheduling is used to ensure performance, then task completion time is guaranteed, but processor operation efficiency decreases
Solution Approach 1:
The patent implements dynamic scheduling that adapts between strict real-time and pseudo real-time modes based on system state. The scheduler monitors task characteristics and system load, dynamically selecting the appropriate scheduling strategy for each task rather than using a fixed approach, thereby resolving the contradiction between performance guarantee and processor efficiency
Solution Approach 2:
The system changes scheduling parameters dynamically by evaluating task characteristics (deterministic vs. non-deterministic execution time) and system state (processor load, buffer status). Based on these parameter evaluations, the scheduler adjusts its behavior to use strict real-time scheduling when needed for performance assurance and pseudo real-time scheduling when processor efficiency is prioritized
2Productivity
If pseudo real-time scheduling is used to improve processor efficiency, then operation efficiency increases, but performance assurance is lost
Solution Approach 1:
The scheduling system dynamically adapts its strategy based on task characteristics. For tasks with deterministic execution times, strict real-time scheduling is applied to ensure performance. For tasks with non-deterministic execution times or when system load is low, pseudo real-time scheduling is used to maximize processor efficiency, thus resolving the contradiction
Solution Approach 2:
The scheduler evaluates multiple parameters including task execution time characteristics, processor load, and buffer status to dynamically change scheduling parameters. This allows the system to switch between scheduling modes based on current conditions, ensuring performance when necessary while optimizing efficiency when possible
3Ease of operation
If tasks are scheduled by fixed priority order without estimation, then scheduling simplicity is maintained, but scheduling efficiency decreases when task loads are biased
Solution Approach 1:
The system performs preliminary estimation of task completion time before scheduling decisions are made. By estimating the execution time of each task in advance based on task characteristics and current system state, the scheduler can make more informed decisions about task allocation and priority assignment, improving scheduling efficiency without significantly increasing complexity
Solution Approach 2:
The scheduling system incorporates feedback mechanisms where actual task execution times are monitored and used to refine future estimates. This feedback loop allows the system to improve its estimation accuracy over time, enabling better scheduling decisions that balance simplicity and efficiency
Data Source
AI summary
An in-vehicle system includes a camera having an encoder encoding video obtained by the camera, an image processing apparatus which receives the encoded video from the camera, and an image recognition processing circuit performing image recognition on decoded video data from the image processing apparatus. The image processing apparatus includes a codec processing circuit which decodes the encoded video, a plurality of image processing circuits which execute tasks in parallel, an estimating circuit which estimates estimation time in which a process of the task is completed in each of the image processing circuit on the basis of the number of access times to a bus which is obtained on the basis of a parameter of decoding used in the codec processing circuit, and a scheduling circuit which schedules tasks to be executed by the plurality of image processing circuit on the basis of the estimation time.