Conditional Fault Modelling in Electronic Circuit Simulation
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Solution Overview
Problem
Current simulation methods for electronic circuit design cannot withdraw or make defects/faults expire during simulation, and do not allow for conditional injection or removal of defects/faults based on electrical or logical states of the simulated circuit.
Innovation Solution
A method and apparatus for simulating electronic circuit designs that allow for the creation of a fault condition, generating a simulation fault model, and controlling the imposition and cessation of the fault condition within the simulation model, enabling simulation of circuit behavior in response to the fault condition's activation and deactivation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a defect/fault is injected during simulation, then the fault condition can be analyzed, but the fault cannot be withdrawn or made to expire during the simulation
Solution Approach 1:
The fault model is transformed from a static permanent defect to a dynamic controllable fault condition. The patent implements time-dependent fault injection where faults can be activated at specific simulation times and deactivated or expire after defined durations, allowing the fault model to adapt its state based on simulation progression and control signals.
Solution Approach 2:
The patent introduces controllable parameters for fault duration and activation timing. By modifying the fault model to accept time-based parameters and control signals, the system can dynamically adjust fault characteristics including when faults become active, how long they persist, and when they are removed, enabling versatile fault analysis scenarios.
2Reliability
If faults are permanently injected during simulation, then fault analysis is possible, but conditional injection or removal based on circuit states is not enabled
Solution Approach 1:
The patent implements feedback mechanisms where the fault model monitors circuit states and control signals to determine fault activation and deactivation. The system continuously evaluates conditions such as simulation time, control signal states, and circuit parameters to dynamically adjust fault presence, enabling conditional fault injection based on real-time circuit behavior and external control inputs.
Solution Approach 2:
The patent introduces control signals and time-based parameters as intermediaries between the simulation environment and the fault model. These intermediaries mediate the fault injection process by carrying information about when faults should be activated, how long they should persist, and under what conditions they should be removed, enabling sophisticated conditional fault analysis.
3Ease of manufacture
If current simulation methods are used, then simple fault injection is possible, but dynamic fault imposition and removal during simulation is not supported
Solution Approach 1:
The patent creates a universal fault model that can operate in multiple modes: permanent fault injection, temporary time-limited faults, and conditional state-based faults. This multi-functional approach allows the same fault model infrastructure to handle diverse simulation scenarios from simple permanent defects to complex dynamic fault sequences, maintaining ease of use while expanding capability.
Data Source
AI summary
A method comprises creating an electronic circuit design having a plurality of electronic components, defining a fault condition imposable during a simulation of the electronic circuit design, and generating a simulation model based on the electronic circuit design. The method also comprises generating a simulation fault model representing the fault condition and executing a simulation of the simulation model to simulate operation of the electronic circuit design. During the execution of the simulation, the method comprises controlling the simulation fault model to begin an imposition of the fault condition within the simulation model, simulating circuit behavior of the simulation model in response to the imposition of the fault condition, controlling the simulation fault model to cease the imposition of the fault condition within the simulation model, and simulating circuit behavior of the simulation model in response to the cessation of the imposition of the fault condition.