Conditional Instruction Processor for Parallel Execution
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Solution Overview
Problem
Existing processors dedicated to searching for elements in lists, such as those used in MPI interfaces, face inefficiencies due to high execution cycles and excessive use of branching, which limits their performance and flexibility, and prevents parallel computing, making them unsuitable for industrial applications.
Innovation Solution
A processor architecture that uses conditional prefixes to control instruction execution, reducing the need for branching and allowing for optimized execution of machine instructions in a single cycle, with the ability to execute multiple operations in parallel, and incorporates a processing chain module to manage instruction flow efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If branching is used to control instruction execution flow, then flexibility and adaptability are improved, but execution time increases and productivity decreases
Solution Approach 1:
The patent extracts the branch prediction and condition evaluation logic from the main instruction execution path by introducing a separate predicate evaluation unit. This allows conditional prefixes to be evaluated in parallel with instruction fetching, removing the sequential dependency that causes cycle penalties in traditional branching approaches.
Solution Approach 2:
The patent performs preliminary evaluation of conditional prefixes during the instruction fetch stage, before the main execution stage. Predicate registers are pre-computed and stored, so that when an instruction is fetched, its conditional execution can be determined immediately without requiring additional cycles for condition checking during execution.
2Measurement precision
If standard ALU and ternary ALU are used for comparison operations, then measurement precision is improved, but parallel computing capability is lost and productivity decreases
Solution Approach 1:
The patent segments the comparison operation into two independent parts: a standard ALU that performs precise arithmetic comparisons, and a separate predicate evaluation unit that handles conditional logic. This segmentation allows both operations to proceed in parallel without interfering with each other, maintaining precision while enabling parallelism.
Solution Approach 2:
The patent merges the results of precise ALU comparisons with predicate register evaluations to determine final instruction execution. By combining these two independent evaluation paths, the system achieves both high precision in comparison operations and high productivity through parallel execution of multiple comparison tasks.
3Productivity
If 164-bit parallel instructions are used, then productivity is improved, but device complexity increases and ease of manufacture worsens
Solution Approach 1:
The patent segments the 164-bit instruction into distinct functional fields: conditional prefix bytes, operation codes, and operand specifications. This segmentation allows the complex instruction format to be processed systematically by dedicated decoder units, reducing the practical complexity despite the large instruction width enabling parallel operations.
Data Source
Figure 1A~1B
Figure 2
Figure 3A~4D
AI summary
A method for processing machine instructions by a processor comprising the following steps: - receiving a machine instruction to be executed, said machine instruction including the identification of at least one first operation to be executed and a conditional prefix representing a condition to be verified in order to execute said at least one first operation, - evaluating said prefix, and - executing or not said at least one first operation identified in said machine instruction, depending on whether said condition is verified or not.