Conditional Non-Branch Instruction Prediction Hardware Translation
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Solution Overview
Problem
Computing device manufacturers and users face challenges in running both x86 and ARM architecture programs due to the need for separate hardware and software investments, leading to potential wasted investments when one architecture becomes dominant over the other, and existing solutions like software translators may not provide sufficient performance.
Innovation Solution
A microprocessor that translates x86 and ARM instructions into microinstructions using a hardware instruction translator, allowing execution by a common execution pipeline, thereby enabling the running of both x86 and ARM architecture programs efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a microprocessor supports both x86 and ARM architectures through hardware translation, then adaptability and versatility are improved, but device complexity increases
Solution Approach 1:
The microprocessor is designed with a universal execution pipeline that can execute instructions from both x86 and ARM architectures through a common hardware translation layer. This multi-functional design allows a single processor to support multiple instruction set architectures, enabling the device to run software compiled for different architectures without requiring separate hardware designs for each architecture.
Solution Approach 2:
A hardware instruction translator is introduced as an intermediary component between the external instruction interfaces and the internal execution pipeline. This translator mediates between the diverse instruction sets (x86, ARM) and the unified execution architecture, converting external instructions into internal microinstructions that the execution pipeline can process uniformly, thereby managing the complexity of supporting multiple architectures.
2Adaptability or versatility
If software translators are used to run x86 and ARM programs, then adaptability is improved, but productivity and performance deteriorate
Solution Approach 1:
The patent replaces software-based translation mechanisms with a hardware-based instruction translation system. Instead of using software translators that interpret and execute instructions through software emulation, the invention implements a hardware translator that directly converts x86 and ARM instructions into microinstructions for the execution pipeline, eliminating the performance penalties associated with software interpretation and providing near-native execution speeds.
Solution Approach 2:
The execution pipeline is designed with multiple copies of execution units that can handle different instruction types simultaneously. The hardware translator generates parallel microinstructions that are executed through duplicated execution paths, allowing efficient concurrent processing of both x86 and ARM instructions without the sequential bottlenecks inherent in software translation approaches.
Data Source
AI summary
A microprocessor processes conditional non-branch instructions that specify a condition and instruct the microprocessor to perform an operation if the condition is satisfied and otherwise to not perform the operation. A predictor provides a prediction about a conditional non-branch instruction. An instruction translator translates the conditional non-branch instruction into a no-operation microinstruction when the prediction predicts the condition will not be satisfied, and into a set of one or more microinstructions to unconditionally perform the operation when the prediction predicts the condition will be satisfied. An execution pipeline executes the no-operation microinstruction or the set of microinstructions. The predictor translates into a second set of one or more microinstructions to conditionally perform the operation when the prediction does not make a prediction. In the case of a misprediction, the translator re-translates the conditional non-branch instruction into the second set of microinstructions.