Runtime Instruction Translation TRIZ Cases
- Conditional Non-Branch Instruction Prediction Hardware Translation
Hardware instruction translator converts conditional non-branch instructions into microinstructions for a common execution pipeline.
- Processor Mapper Translates Dependent Instructions
A processor mapper translates dependent operations into new independent instructions using source registers.
- Heterogeneous Processor Instruction Translation
A translation system segments program instructions for execution across heterogeneous processors.
- Non-atomic Microinstruction Scheduling for Floating-Point Rounding
A microprocessor translates rounding instructions into separate microinstructions dispatched out-of-order to reduce execution latency.
- Shared SFU Architecture for AI Chip Area Reduction
A shared special function unit architecture reduces chip area in artificial intelligence processors.
- Memory Controller Data Conversion Unit for Threshold Voltage Distribution
A memory controller data conversion unit randomizes host data using XOR operations with reference bits before storage.