Non-atomic Microinstruction Scheduling for Floating-Point Rounding
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Solution Overview
Problem
Existing microprocessor designs face challenges in efficiently executing the ROUND instruction for floating-point operations due to high latency and unnecessary circuit component utilization, particularly when converting between floating-point and integer values, which is exacerbated by the need for special-purpose hardware or sequential circuit connections.
Innovation Solution
A microprocessor architecture that translates the ROUND instruction into two microinstructions (XROUND1 and XROUND2) allowing for out-of-order dispatch and execution, minimizing latency by separating operations into minimal circuit groups and avoiding additional architectural state, thus enabling efficient execution without special-purpose hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential circuit connections are used to perform floating-point to integer conversion and integer to floating-point conversion, then the required conversion capabilities are provided, but the latency is high and circuit utilization is poor
Solution Approach 1:
The patent divides the ROUND instruction execution into two separate microinstructions: XROUND1 performs the floating-point to integer conversion, and XROUND2 performs the integer to floating-point conversion. This segmentation allows the conversions to be executed in separate circuit groups rather than sequential connections, reducing latency and improving circuit utilization.
2Reliability
If special-purpose hardware is provided for floating-point to integer conversion and integer to floating-point conversion, then the conversion capabilities are available, but valuable die space is consumed
Solution Approach 1:
The patent designs the conversion circuits to be multi-functional, allowing the same circuit groups to handle both floating-point to integer conversion and integer to floating-point conversion operations. This eliminates the need for separate special-purpose hardware for each conversion type, reducing die space consumption while maintaining full conversion capabilities.
3Area of stationary object
If maximally utilized circuit elements are used rather than special-purpose hardware, then die space is saved, but any calculation not requiring some portion of the sequential connection is penalized with intrinsic delay
Solution Approach 1:
The patent implements dynamic scheduling that allows microinstructions to be dispatched and executed out of order based on circuit availability. The XROUND1 and XROUND2 microinstructions can be executed in separate circuit groups at different times, with the scheduler optimizing the execution sequence to minimize delays while maximizing circuit utilization.
4Loss of time
If floating-point to integer conversion and integer to floating-point conversion are scheduled temporally sequentially using separate circuit groups, then total latency per calculation is reduced, but additional architectural state and special-case logic are required
Solution Approach 1:
The patent uses the existing intermediate result from the floating-point to integer conversion as the input for the integer to floating-point conversion without requiring additional architectural state to store intermediate values. The circuit groups share the intermediate data through standard data paths, avoiding the need for special-purpose storage elements or additional state management logic.
Data Source
AI summary
A microprocessor executes an instruction specifying a floating-point input operand having a predetermined size and that instructs the microprocessor to round the floating-point input operand to an integer value using a rounding mode and to return a floating-point result having the same predetermined size. An instruction translator translates the instruction into first and second microinstructions. An execution unit executes the first and second microinstructions. The first microinstruction receives as an input operand the instruction floating-point input operand and generates an intermediate result from the input operand. The second microinstruction receives as an input operand the intermediate result of the first microinstruction and generates the floating-point result of the instruction from the intermediate result. The intermediate result is the same predetermined size as the instruction floating-point input operand. The microprocessor executes the first and second microinstructions such that the commencement of their executions may have indeterminate separation in time.