Confidence-Driven Selective Instruction Predication

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Solution Overview

Problem

Processor inefficiencies arise from conditional branch instructions, as processors delay adding instructions into the pipeline until the branch condition is calculated, leading to significant delays and inefficiencies, with existing branch prediction and instruction predication techniques having limitations and introducing additional inefficiencies.

Innovation Solution

A method that dynamically converts non-predicated instructions to predicated instructions based on a branch prediction confidence level, using a branch prediction unit to determine the confidence level and an instruction fetch unit to fetch and convert instructions when the confidence is low, allowing for efficient execution of both branch paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If branch prediction is used to guess which branch will be taken, then processor efficiency is improved by reducing pipeline stalls, but misprediction penalties occur when the prediction is incorrect

Engineering Contradiction:
Improveprocessor efficiencyVSAvoidprediction accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically switches between branch prediction and instruction predication based on real-time confidence levels. When confidence is high, branch prediction is used for efficiency. When confidence is low, the system transitions to instruction predication to ensure correctness, making the approach adaptive to varying conditions rather than static

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameter from binary branch prediction to confidence-driven selective predication. By introducing confidence levels as a controlling parameter, the system can adjust its behavior continuously based on the reliability of branch predictions, transitioning between different execution strategies

Inventive Principle:
Principle #35Parameter changes

2Productivity

If instruction predication is used to execute all related instructions in the pipeline, then processor efficiency is improved by eliminating branch delays, but device complexity increases due to additional conversion logic

Engineering Contradiction:
Improveprocessor efficiencyVSAvoidconversion logic complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Instead of applying instruction predication uniformly to all instructions, the system applies it locally and selectively only to instructions following low-confidence branches. This localized approach reduces the overall complexity burden while maintaining efficiency where needed

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The conversion from non-predicated to predicated instructions is performed dynamically at runtime based on confidence levels rather than being a static compiler optimization. This allows the system to adapt the complexity level to actual execution conditions

Inventive Principle:
Principle #15Dynamics

3Device complexity

If processors wait until the branch instruction is executed to determine which instructions to fetch, then simplicity is maintained, but significant pipeline idle time occurs

Engineering Contradiction:
Improveprocessor simplicityVSAvoidpipeline idle time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The system performs preliminary action by converting instructions to predicated form before execution when low confidence is detected. This advance preparation allows the pipeline to be filled with appropriate instructions without waiting for branch resolution, eliminating idle time while maintaining relative simplicity

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10162635B2Confidence-driven selective predication of processor instructions
Publication Date: 2018.12.25 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10162635B2 patent drawing
  • US10162635B2 patent drawing
  • US10162635B2 patent drawing

AI summary

An apparatus includes a network interface, memory, and a processor. The processor is coupled with the network interface and memory. The processor is configured to determine that an instruction instance is a branch instruction instance. Responsive to a determination that an instruction instance is a branch instruction instance, the processor is configured to obtain a branch prediction for the branch instruction instance and a confidence value of the branch prediction. The processor is further configured to determine that the confidence for the branch prediction is low based on the confidence value, and responsive to such a determination, generate predicated instruction instances based on the branch instruction instance.