Microprocessor Mode Indicator for x86 ARM MSR Access

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Computing device manufacturers and users face challenges in running both x86 and ARM architecture programs due to the need for separate hardware and software support, leading to wasted investments when one architecture becomes dominant over the other, and existing solutions like software translators may not provide sufficient performance.

Innovation Solution

A microprocessor capable of running both x86 and ARM instruction set architectures, featuring a mode indicator and model-specific registers accessible via specific instructions, along with a hardware instruction translator that translates instructions into microinstructions for direct execution, enabling seamless operation between the two architectures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate hardware designs are used for x86 and ARM architectures, then each architecture can be optimized for its specific performance requirements, but manufacturing complexity and resource waste increase when one architecture becomes dominant

Engineering Contradiction:

Improvearchitectural performance optimizationVSAvoidhardware design complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a single microprocessor that can execute both x86 and ARM instruction set architectures through a unified microarchitecture core. The processor includes a mode indicator and model-specific registers that enable it to switch between architectures, allowing one hardware device to serve multiple functions and reduce the need for separate dedicated processors for each architecture.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces a hardware instruction translator as an intermediary component that converts x86 or ARM instructions into the processor's internal microinstructions. This translator layer enables the single microprocessor to accommodate multiple instruction sets without requiring separate execution pipelines for each architecture, thereby reducing overall hardware complexity while maintaining architectural optimization benefits.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Device complexity

If software translators are used to run both architectures on a single processor, then hardware resource waste is reduced, but execution performance deteriorates

Engineering Contradiction:

Improvehardware resource utilizationVSAvoidexecution performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent replaces software-based translation mechanisms with a hardware instruction translator implemented in circuitry. This hardware translator operates at the instruction level, converting x86 or ARM instructions directly into microinstructions for the execution pipeline. By moving the translation function from software to hardware, the system achieves both reduced hardware resource waste (single processor supports both architectures) and maintained execution performance (hardware-level translation overhead is minimal).

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If a single microprocessor supports both x86 and ARM architectures, then hardware resource waste is reduced and versatility improves, but the complexity of supporting multiple instruction sets increases

Engineering Contradiction:

Improvemulti-architecture supportVSAvoidinstruction set support complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the instruction translation process into distinct components: a mode indicator that identifies the current architecture, model-specific registers that store architecture-specific state, and a hardware instruction translator that processes instructions according to the selected mode. This segmentation allows the processor to manage multiple instruction sets through modular organization, reducing the overall complexity of supporting both x86 and ARM architectures.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a universal microprocessor core that can execute both x86 and ARM instruction set architectures. The processor includes a mode indicator and model-specific registers that enable it to switch between architectures, allowing one hardware device to serve multiple functions and reduce the need for separate dedicated processors for each architecture.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9043580B2Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)

Publication Date: 2015.05.26 VIA TECH INC

AI summary

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.