Processor Mapper Translates Dependent Instructions

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Solution Overview

Problem

Processors employing out-of-order execution face increased execution latency due to dependency disambiguation techniques, which reduce processing efficiency by requiring dependent instructions to wait for the execution of preceding instructions.

Innovation Solution

A processor mapper translates dependent operations into new operations that use source registers from the dependent operation, making them independent of other pending operations, allowing for out-of-order execution without waiting for the completion of the initial operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a scheduler is used to ensure that a dependent instruction is not executed until after execution of the instruction from which it depends, then execution accuracy is maintained, but execution latency of the dependent instruction increases

Engineering Contradiction:
Improveexecution accuracyVSAvoidexecution latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The mapper performs preliminary translation of dependent instructions into independent instructions before execution. By translating instruction B (which depends on instruction A) into instruction B' that directly uses source operands of instruction A, the system eliminates the need to wait for instruction A to complete, thus reducing execution latency while maintaining correctness through the translation process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The mapper acts as an intermediary between the instruction stream and the execution units. It translates dependent instructions into equivalent independent instructions, mediating the dependency relationship by transforming it into a form that can be executed out-of-order while preserving the original program semantics

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If out-of-order execution is employed to enhance processing efficiency, then processor throughput increases, but execution latency of dependent instructions increases due to waiting for preceding instructions

Engineering Contradiction:
Improveprocessor throughputVSAvoidexecution latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The mapper performs preliminary translation of dependent instructions into independent instructions before they enter the execution pipeline. This advance transformation enables the instructions to be executed immediately without waiting for their dependencies, thus maintaining low latency while allowing aggressive out-of-order execution for high throughput

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The instruction translation process segments the dependency relationship by separating the source operand usage from the execution order. By translating instruction B to use source operands directly rather than waiting for instruction A's result, the system segments the dependency chain and enables parallel execution of previously dependent instructions

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9733941B2Technique for translating dependent instructions
Publication Date: 2017.08.15 ADVANCED MICRO DEVICES INC
  • US9733941B2 patent drawing
  • US9733941B2 patent drawing
  • US9733941B2 patent drawing

AI summary

In response to determining an operation is a dependent operation, a mapper of a processor determines the source registers of the operation from which the dependent operation depends. The mapper translates the dependent operation to a new operation that uses as its source operands at least one of the determined source registers and a source register of the dependent operation. The new operation is independent of other pending operations and therefore can be executed without waiting for execution of other operations, thus reducing execution latency.