Microcode Patch Fuse Banks for Pipeline Delay Reduction
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Solution Overview
Problem
Current microcode patch techniques in microprocessors introduce pipeline delays and are inflexible, limiting performance and flexibility, especially when replacing microcode instructions or implementing complex patches.
Innovation Solution
A microcode patch apparatus and method utilizing fuse banks and an array controller to store and load patches before instruction execution, allowing real-time one-to-one and one-to-many microcode patches without pipeline delays, and enabling patching during fabrication or in the field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If microcode patch techniques are implemented to correct errors in microcode ROM, then reliability is improved, but pipeline delays are introduced and productivity deteriorates
Solution Approach 1:
The patent implements a patch loader that loads patch data from fuse banks into patch buffer memory during the reset initialization phase, before the instruction pipeline begins execution. This preliminary action ensures that when microcode patches are needed during operation, they are already loaded and ready, eliminating pipeline delays that would occur if patches were loaded on-demand during instruction execution.
Solution Approach 2:
The patent introduces a patch buffer memory as an intermediary component between the fuse banks and the microcode ROM. This buffer acts as a mediator that holds patch data in ready-state, allowing the microcode ROM to be patched without causing pipeline interruptions. The buffer memory decouples the patch application process from the instruction execution flow, maintaining productivity while improving reliability.
2Reliability
If traditional microcode patching methods are used, then error correction is achieved, but flexibility deteriorates due to limited patching options
Solution Approach 1:
The patent implements a dynamic patching system where the microcode ROM can be patched at multiple stages: during fabrication (via fuse banks), during system initialization (via patch loader from external memory), and potentially during runtime (via patch buffer). This dynamic capability allows the system to adapt to different error conditions and operational requirements, significantly improving flexibility compared to static traditional patching methods.
Solution Approach 2:
The patent segments the patching functionality into distinct components: fuse banks for fabrication-time patches, patch loader for initialization-time patches, and patch buffer for runtime patches. This segmentation allows each component to handle specific types of patching operations, providing versatility in choosing the appropriate patching method based on the situation while maintaining system reliability.
3Adaptability or versatility
If microcode patches are loaded during instruction execution, then flexibility is maintained, but pipeline delays occur and productivity decreases
Solution Approach 1:
The patent loads patch data into the patch buffer memory during the reset initialization phase, which occurs before the instruction pipeline begins executing user instructions. This preliminary loading action ensures that when patches are needed during instruction execution, they are already in the buffer and can be applied immediately without interrupting the instruction throughput, thus maintaining both flexibility and productivity.
4Quantity of substance
If fuse banks are programmed during fabrication to store patch data, then patch capacity is increased, but device complexity increases
Solution Approach 1:
The patent designs the fuse banks to serve multiple functions: they can store patch data for microcode ROM correction, and the same fuse bank infrastructure can potentially store configuration data for other system parameters. This multi-functionality increases patch storage capacity without proportionally increasing device complexity, as the same hardware infrastructure supports multiple uses.
Data Source
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AI summary
A patch apparatus includes fuse banks, one or more configuration fuse banks, and an array controller. The fuse banks are configured to store associated patch records that are employed to patch microcode or machine state circuits in the microprocessor or to store associated control data entities that are employed to program control circuits in the microprocessor. The configuration fuse banks are encoded to indicate whether each of the plurality of fuse banks is programmed with one of the associated patch records or with one of the associated control data entities. The array controller reads the fuse banks, and provides the associated patch records to a patch loader or the associated control data entities to control circuits in the microprocessor. The patch loader provides patches corresponding to the associated patch records, as prescribed, to designated target patch mechanisms in the microprocessor. The patch loader provides the patches to the designated target patch mechanisms following transition of a microprocessor reset signal and prior to execution of instructions stored in a BIOS ROM.