Encapsulating Long Instructions in Short Instruction Sets

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Solution Overview

Problem

Reduced instruction sets cannot express long instructions optimized for hardware, leading to slower processing and requiring separate compiler development, increasing complexity and time to market.

Innovation Solution

Encapsulating long instructions into sets of short instructions using identifiers to enable their execution on processors, allowing each bit of the long instruction to be included in the short instructions, and using format bits to determine assembly methods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If long instructions are used to express high-level specific instructions, then processing speed is improved, but code size increases and processor complexity increases

Engineering Contradiction:

Improveprocessing speedVSAvoidprocessor complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent segments long instructions into multiple short instruction components. Each long instruction is divided into several short instructions that can be processed sequentially by the processor, maintaining fast processing speeds while allowing the processor to remain optimized for short instruction handling.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements nesting by embedding multiple levels of instruction encoding within short instruction formats. Short instructions contain encoded representations of longer instruction sequences, allowing the processor to execute complex operations through nested instruction structures without requiring physical long instruction support.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Device complexity

If reduced instruction sets with short instructions are used, then processor complexity is reduced, but processing speed decreases for high-level specific instructions

Engineering Contradiction:

Improveprocessor complexityVSAvoidprocessing speed

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The patent introduces an intermediary encoding mechanism that translates short instruction sequences into effective long instruction operations. The processor remains simple and short-instruction-oriented, but the intermediary encoding layer enables efficient execution of high-level specific instructions by interpreting sequences of short instructions as cohesive operational units.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If a separate compiler is designed for reduced instruction sets, then compatibility with short instructions is improved, but development time increases

Engineering Contradiction:

Improveinstruction set compatibilityVSAvoiddevelopment time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent creates a universal instruction encoding system where short instructions can serve multiple functions - both as standalone simple operations and as components of encoded long instructions. This multi-functionality allows existing compilers to work with the reduced instruction set while still accessing high-level specific instructions through the encoding mechanism, eliminating the need for completely separate compiler development.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9152421B2Assembling long instruction encapsulated in short instructions according to method identified by format bits

Publication Date: 2015.10.06 QUALCOMM TECH INT

AI summary

A method of encapsulating a long instruction in a set of short instructions for execution on a processor, the long instruction having k bits and each short instruction having l bits where l<k, includes assembling a first portion of the long instruction and a first identifier to form a first instruction of the set of short instructions; and assembling a second portion of the long instruction and a second identifier to form a second instruction of the set of short instructions; wherein at least one of the first and second identifiers is for identifying to the processor that the set of short instructions encapsulates the long instruction.