Microprocessor Hardware Registers for ARM x86 ISA Register Access
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Solution Overview
Problem
Computing device manufacturers and users face challenges in running both x86 and ARM architecture programs due to investment wastage when one architecture becomes dominant over the other, as existing solutions like software translators may not provide sufficient performance for many users.
Innovation Solution
A microprocessor that includes hardware registers for both Intel 64 Architecture and ARM Architecture general-purpose registers, allowing switching between IA-32 and ARM operating modes to run x86 and ARM programs seamlessly, with a hardware instruction translator that translates instructions into microinstructions for direct execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a microprocessor supports both x86 and ARM architectures, then versatility is improved, but device complexity increases
Solution Approach 1:
The microprocessor is designed to execute both x86 and ARM instructions using a unified execution architecture. The processor includes a translation lookaside buffer (TLB) that can translate either x86 or ARM virtual addresses to physical addresses, and an execution unit that can fetch and execute instructions from either architecture, making the processor universal and capable of running software for both architectures on a single device.
Solution Approach 2:
The patent introduces a translation layer (TLB) as an intermediary between the virtual address space and physical address space. This TLB maintains translation tables for both x86 and ARM architectures, allowing the processor to efficiently translate addresses from either architecture without requiring separate physical address spaces or complex address translation mechanisms.
2Adaptability or versatility
If software translators are used to run x86 programs on ARM processors, then adaptability is improved, but productivity deteriorates due to performance loss
Solution Approach 1:
The patent merges the execution capabilities of both x86 and ARM architectures into a single execution unit. Instead of using software translation to emulate x86 instructions on an ARM processor (which causes performance loss), the microprocessor directly executes both architectures using the same execution pipeline, eliminating the performance penalty associated with software translation while maintaining adaptability.
3Productivity
If a microprocessor executes instructions directly without translation, then productivity is improved, but adaptability worsens
Solution Approach 1:
The microprocessor employs dynamic address translation through the TLB, which can switch between x86 and ARM translation tables based on the current instruction set being executed. This dynamic translation capability allows the processor to maintain fast direct execution for the current architecture while remaining adaptable to execute both x86 and ARM programs, resolving the contradiction between execution speed and versatility.
Data Source
AI summary
A microprocessor includes hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. The microprocessor also includes hardware registers that instantiate the ARM Architecture GPRs. In response to an ARM MRRC instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate two of the ARM GPRs registers. In response to an ARM MCRR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate two of the ARM Architecture GPRs registers. The hardware registers may be shared by the two Architectures.