Future Execution Prefetching via Value Prediction
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Solution Overview
Problem
Modern microprocessors face inefficiencies due to long memory latency, which existing prefetching techniques struggle to address effectively, especially for irregular codes, requiring complex hardware and not adequately capturing cache misses that exhibit irregular behavior.
Innovation Solution
The future execution technique involves dynamically creating a prefetching thread by copying committed instructions from an active thread and using a value predictor to replace predictable instructions with predicted results, allowing a second processor core to execute this thread and prefetch data, thereby reducing memory access time for the original thread.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If execution-based prefetching techniques use additional execution pipelines or idle thread contexts to execute helper threads, then prefetching coverage is improved, but hardware complexity increases
Solution Approach 1:
The patent creates a copy of the original thread's instruction stream and executes it as a helper thread on an idle core. This copying approach allows the helper thread to prefetch data without requiring complex specialized hardware structures, as the instruction stream is simply replicated and executed independently
Solution Approach 2:
The patent utilizes idle processor cores that already exist in the system for their intended purpose of executing additional threads. By repurposing these idle cores to execute helper threads for prefetching, the system avoids adding dedicated specialized hardware while achieving enhanced prefetching capabilities
2Productivity
If static software helper threads are used, then code acceleration is achieved, but code size increases and instruction-cache efficiency decreases
Solution Approach 1:
The patent extracts only the essential instruction stream from the original thread to create the helper thread, rather than duplicating entire static helper thread implementations. This extraction approach minimizes the additional code size while maintaining the acceleration benefit
Solution Approach 2:
The patent employs dynamic creation of helper threads based on runtime conditions rather than static pre-defined helper threads. The helper threads are created when needed and can be dynamically adjusted, allowing the system to optimize code size by only including necessary instructions rather than pre-compiled static helper code
3Measurement precision
If helper threads are constructed dynamically with specialized hardware analyzer, then prefetching accuracy is improved, but hardware complexity and verification cost increase
Solution Approach 1:
The patent copies the original thread's instruction stream to create the helper thread, eliminating the need for specialized hardware analyzers to extract and analyze instruction patterns. The copying mechanism inherently preserves the original execution patterns, achieving accurate prefetching without complex analysis hardware
Solution Approach 2:
The original instruction stream serves as its own template for creating the helper thread. By copying and executing the same instruction stream, the system automatically captures the correct execution patterns and data dependencies without requiring external hardware analysis or verification
Data Source
AI summary
A prefetching technique referred to as future execution (FE) dynamically creates a prefetching thread for each active thread in a processor by simply sending a copy of all committed, register-writing instructions in a primary thread to an otherwise idle processor. On the way to the second processor, a value predictor replaces each predictable instruction with a load immediate instruction, where the immediate is the predicted result that the instruction is likely to produce during its nth next dynamic execution. Executing this modified instruction stream (i.e., the prefetching thread) in another processor allows computation of the future results of the instructions that are not directly predictable. This causes the issuance of prefetches into the shared memory hierarchy, thereby reducing the primary thread's memory access time and speeding up the primary thread's execution.