Conditional Store Instructions in Out-of-Order Microprocessors
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Solution Overview
Problem
Computing device manufacturers and users face challenges in running both ×86 and ARM architecture programs due to the dominance of one architecture over the other, leading to wasted investments and resource inefficiencies, as existing solutions like software translators may not provide sufficient performance for many users.
Innovation Solution
A microprocessor with an instruction set architecture that defines a conditional store instruction, including a store queue and register file, translates this instruction into microinstructions for an out-of-order execution pipeline, allowing efficient execution based on condition flags, enabling the microprocessor to run both ×86 and ARM architecture programs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software translators are used to run both ×86 and ARM architecture programs, then architectural versatility is improved, but execution performance deteriorates
Solution Approach 1:
The microprocessor implements a unified execution pipeline that can execute instructions from multiple instruction set architectures (×86 and ARM) natively, eliminating the need for separate software translators. The conditional store instruction mechanism enables the same hardware to handle different architectural requirements efficiently, achieving both versatility and high performance.
Solution Approach 2:
The patent replaces software-based translation mechanisms with a hardware-level solution. By implementing conditional store instructions directly in the instruction set architecture and using hardware condition flags (NZCV) to control store operations, the system eliminates the need for software translators and achieves native execution performance for multiple architectures.
2Productivity
If conditional store instructions are implemented with hardware support, then execution speed is improved, but device complexity increases
Solution Approach 1:
The conditional store instruction merges the store operation with condition evaluation in a single instruction. The hardware condition flags (NZCV) are already present in the processor architecture, so the patent integrates the conditional logic into the existing execution pipeline rather than adding separate condition evaluation hardware, thereby minimizing complexity increase.
Solution Approach 2:
The execution pipeline automatically uses the hardware condition flags (NZCV) to determine whether to execute the store operation without requiring additional control logic or complex decision-making circuits. The condition flags themselves serve as the control signal, simplifying the implementation.
3Productivity
If out-of-order execution is used for conditional instructions, then productivity is improved, but reliability concerns arise
Solution Approach 1:
The patent calculates the effective address for the conditional store instruction before the actual store operation. By preparing the address calculation in advance using the base register and offset, and validating it through the store queue mechanism, the system ensures correct memory location access while maintaining out-of-order execution benefits.
Solution Approach 2:
The execution pipeline uses the hardware condition flags (NZCV) as feedback to control whether the store operation should execute. This feedback mechanism ensures that only appropriate store operations are executed, maintaining program correctness and reliability while allowing out-of-order execution to proceed.
Data Source
AI summary
An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.