Conductance Mapping for Neural Network Synapse Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory architecture designs face challenges in scalability and energy efficiency for machine learning applications, particularly in training and inference, and struggle with effectively implementing neural networks on resource-limited physical substrates.
Innovation Solution
The implementation of configurable neural networking schemes using spiking neural networks (SNN) with non-volatile memories (NVM) such as RRAM, MRAM, and CeRAM, which enable energy-efficient online training by leveraging event-driven computations and analog domain calculations, and utilize resistive intersecting crossbars for efficient conductance mapping and weight adjustments based on Spike-Timing-Dependent Plasticity (STDP) learning rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory architecture designs are used for machine learning, then implementation is straightforward with existing technologies, but scalability and energy efficiency deteriorate for training and inference operations
Solution Approach 1:
The patent replaces conventional digital computing architectures with neuromorphic computing systems that mimic biological neural networks. This substitution enables parallel processing of neural network operations directly in hardware, dramatically improving scalability and reducing energy consumption for machine learning training and inference compared to traditional sequential digital processing
Solution Approach 2:
The patent utilizes analog conductance values in crossbar memory devices to represent neural network weights, enabling continuous weight adjustments during training. This parameter change from discrete digital values to continuous analog conductance allows for efficient gradient descent optimization and significantly reduces the energy required for weight updates compared to conventional digital systems
2Use of energy by stationary object
If neuromorphic architecture is implemented to mimic human brain architecture, then energy efficiency improves, but implementation difficulty increases due to resource limitations on physical substrates
Solution Approach 1:
The patent implements a unified crossbar architecture that serves multiple functions: storing synaptic weights via conductance values, performing parallel matrix-vector multiplications for neural network inference, and enabling online learning through conductance modulation. This multi-functionality reduces implementation complexity compared to separate dedicated hardware for each operation while maintaining high energy efficiency
Solution Approach 2:
The neuromorphic system performs computations directly where data is stored in the crossbar memory, eliminating the need for data movement between separate storage and processing units. This compute-in-memory approach enables the system to serve itself by performing neural network operations in-place, reducing implementation complexity and improving energy efficiency simultaneously
3Use of energy by stationary object
If analog domain calculations are used for neural network operations, then energy efficiency improves through event-driven computations, but precision deteriorates due to device variability and noise
Solution Approach 1:
The patent implements feedback mechanisms where the system measures actual conductance values in the crossbar and uses this information to adjust subsequent operations. This feedback enables compensation for device variability and noise, maintaining computational precision while retaining the energy efficiency benefits of analog calculations
Solution Approach 2:
The system performs preliminary calibration and characterization of crossbar device conductance values before neural network operations. This preliminary action establishes baseline measurements that are used to compensate for device variability during actual computations, ensuring precision is maintained despite using analog domain calculations
4Productivity
If conductance mapping is used for weight representation, then computational efficiency improves through parallel operations, but mapping complexity increases for accurate weight-to-conductance conversion
Solution Approach 1:
The patent performs preliminary measurement and characterization of crossbar device conductance properties during fabrication or initialization. This preliminary action creates a mapping table or calibration data that simplifies subsequent weight-to-conductance conversions, reducing mapping complexity while maintaining computational efficiency through parallel operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach leads to improved energy efficiency and scalability by performing computations only where necessary, reducing energy consumption and enhancing the implementation of dense deep neural networks, while allowing for high-precision matrix-vector multiplications in low-precision programmed systems, thus overcoming limitations in device precision and system noise.
Implementation Method 1
designed with RRAM, MRAM, STT-MRAM and/or CeRAM NVM synapse cells
Implementation Method 2
magnetic RAM (MRAM), spin-transfer-torque magnetic RAM (STT-MRAM)
Implementation Method 3
utilize resistive intersecting crossbars for efficient conductance mapping
Implementation Method 4
resistive intersecting crossbars for efficient conductance mapping and weight adjustments
Implementation Method 5
weight adjustments based on Spike-Timing-Dependent Plasticity (STDP) learning rules
Data Source
AI summary
Various implementations described herein are directed to a device having neural network circuitry with an array of synapse cells arranged in columns and rows. The device may have input circuitry that provides voltage to the synapse cells by way of row input lines for the rows in the array. The device may have output circuitry that receives current from the synapse cells by way of column output lines for the columns in the array. Also, conductance for the synapse cells in the array may be determined based on the voltage provided by the input circuitry and the current received by the output circuitry.